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Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional

Full error: Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "in" into its bus The right number of resources seem to be used but I find this...
Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Many thanks for the fast reply. This would be so much neater if I could retain the 2D array.

My concern was that this would affect synthesis and good to know that it won't. I can live with a warning!

KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Sure. I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Thanks.

Best regards,

KhaiY