Forum Discussion
Inferring Simple dual-port RAM with write enable & read enable
- 2 years ago
Hi,
read-during-write behaviour is only critical for same address applied to read andwrite port simultaneously.
MAX10 M9K as well as e.g. Arria 10 M20K support "old-data" or "don't care" mode for single clock DP RAM. "new data" isn't supported and needs to be emulated by additional registers and read data mux if required in your application.
I don't recognize at first sight if read-during-write behaviour is relevant for you application. It can be best checked in a simulation.
My previous post needs to be corrected. It's not a problem of missing rden port, M9K actually has a rden port and the device handbook suggests to use if for power saving.
Problem is the doubled connection of rden in your code
always @ (posedge wclk) beginif (we) beginram[waddr] <= wdata;endif (re) beginr_rdata_1P <= ram[raddr];r_rdata_2P <= r_rdata_1P;endendgenerateif (OUTPUT_REG == "TRUE")assign rdata = r_rdata_2P;elseassign rdata = r_rdata_1P;endgenerate
Only the second assignment should be gated by (re). Doing so stops dual-clock RAM inference and removes the warnigs.
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