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AUDIY's avatar
AUDIY
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Inferring Simple dual-port RAM with write enable & read enable

I compiled the project with Single-clock simple dual-port RAM with write & read enable like attached quartus project. But the compiler output the warning like below. Warning (276027): Inferred du...
Hdl
  • FvM's avatar
    FvM
    2 years ago

    Hi,
    read-during-write behaviour is only critical for same address applied to read andwrite port simultaneously.

    MAX10 M9K as well as e.g. Arria 10 M20K support "old-data" or "don't care" mode for single clock DP RAM. "new data" isn't supported and needs to be emulated by additional registers and read data mux if required in your application.

    I don't recognize at first sight if read-during-write behaviour is relevant for you application. It can be best checked in a simulation.

    My previous post needs to be corrected. It's not a problem of missing rden port, M9K actually has a rden port and the device handbook suggests to use if for power saving.

    Problem is the doubled connection of rden in your code


    always @ (posedge wclk) begin

    if (we) begin
    ram[waddr] <= wdata;
    end
    if (re) begin
    r_rdata_1P <= ram[raddr];
    r_rdata_2P <= r_rdata_1P;
    end
    end
    generate
    if (OUTPUT_REG == "TRUE")
    assign rdata = r_rdata_2P;
    else
    assign rdata = r_rdata_1P;
    endgenerate

    Only the second assignment should be gated by (re). Doing so stops dual-clock RAM inference and removes the warnigs.
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,
read-during-write behaviour is only critical for same address applied to read andwrite port simultaneously.

MAX10 M9K as well as e.g. Arria 10 M20K support "old-data" or "don't care" mode for single clock DP RAM. "new data" isn't supported and needs to be emulated by additional registers and read data mux if required in your application.

I don't recognize at first sight if read-during-write behaviour is relevant for you application. It can be best checked in a simulation.

My previous post needs to be corrected. It's not a problem of missing rden port, M9K actually has a rden port and the device handbook suggests to use if for power saving.

Problem is the doubled connection of rden in your code


always @ (posedge wclk) begin

if (we) begin
ram[waddr] <= wdata;
end
if (re) begin
r_rdata_1P <= ram[raddr];
r_rdata_2P <= r_rdata_1P;
end
end
generate
if (OUTPUT_REG == "TRUE")
assign rdata = r_rdata_2P;
else
assign rdata = r_rdata_1P;
endgenerate

Only the second assignment should be gated by (re). Doing so stops dual-clock RAM inference and removes the warnigs.
AUDIY's avatar
AUDIY
Icon for New Contributor rankNew Contributor
2 years ago

Hi,

Thank you for your solution and I checked the warning is removed.

I designed this project that when (re) is toggled (1'b1 -> 1'b0) when written address is the same as read address.
So I think this warning is no-problem actually but I keep in mind this solution.

Thanks,
AUDIY.