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AUDIY's avatar
AUDIY
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Inferring Simple dual-port RAM with write enable & read enable

I compiled the project with Single-clock simple dual-port RAM with write & read enable like attached quartus project. But the compiler output the warning like below. Warning (276027): Inferred du...
Hdl
  • FvM's avatar
    FvM
    2 years ago

    Hi,
    read-during-write behaviour is only critical for same address applied to read andwrite port simultaneously.

    MAX10 M9K as well as e.g. Arria 10 M20K support "old-data" or "don't care" mode for single clock DP RAM. "new data" isn't supported and needs to be emulated by additional registers and read data mux if required in your application.

    I don't recognize at first sight if read-during-write behaviour is relevant for you application. It can be best checked in a simulation.

    My previous post needs to be corrected. It's not a problem of missing rden port, M9K actually has a rden port and the device handbook suggests to use if for power saving.

    Problem is the doubled connection of rden in your code


    always @ (posedge wclk) begin

    if (we) begin
    ram[waddr] <= wdata;
    end
    if (re) begin
    r_rdata_1P <= ram[raddr];
    r_rdata_2P <= r_rdata_1P;
    end
    end
    generate
    if (OUTPUT_REG == "TRUE")
    assign rdata = r_rdata_2P;
    else
    assign rdata = r_rdata_1P;
    endgenerate

    Only the second assignment should be gated by (re). Doing so stops dual-clock RAM inference and removes the warnigs.
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago
Intel block RAM doesn't provide read enable, it's apparently emulated by clock enable in your design, respectively needing two clocks.

According to my experience, RAM read enable is rarely necessary in designs, the function can be achieved by other means like separate output register.
AUDIY's avatar
AUDIY
Icon for New Contributor rankNew Contributor
2 years ago

Thank you for your answer.

I try changing design you recommend.

Thanks,
AUDIY