Forum Discussion
New ContributorInferring RAM with byte-enable from parametrized SystemVerilog
Thanks for your design, after investigation, this user guide only can be used of Quartus Pro related devices.(Statix 10, Agilex 7 and etc).
It will not be applicable for Std edition, https://www.intel.com/content/www/us/en/docs/programmable/683082/24-3/ram-with-byte-enable-signals.html#mwh1409959589276__example_SystemVerilog_Simple
In your Quartus, if your right click and insert template, you will see this example in standard edition.
Super ContributorHi,
found a better solution for Quartus Std., use generate for instead of simple for loop.
genvar i; generate for (i = 0; i < NUM_BYTES; i++) begin : gen_be always@(posedge clk) if(we & be[i]) ram[waddr][i] <= wdata[i*BYTE_WIDTH +: BYTE_WIDTH]; end endgenerate always@(posedge clk) begin q <= ram[raddr]; end
Regards
Frank
k_dzAlthough it uses dedicated memory resources and does not require repeating a single line, I'm not sure it's a better solution. In my testing it maps to NUM_BYTES separate M10K blocks and I couldn't find a way to convert it to write-first/"read new data", as Quartus requires blocking assignments to infer such same-port read-during-write behaviour.
I know that I can just generate N separately driven RAM modules, each storing the i-th byte forming N-byte word, but that is just wasteful in many cases.
