Inferring RAM with byte-enable from parametrized SystemVerilog

Thanks for your design, after investigation, this user guide only can be used of Quartus Pro related devices.(Statix 10, Agilex 7 and etc).

It will not be applicable for Std edition, https://www.intel.com/content/www/us/en/docs/programmable/683082/24-3/ram-with-byte-enable-signals.html#mwh1409959589276__example_SystemVerilog_Simple

In your Quartus, if your right click and insert template, you will see this example in standard edition.