Forum Discussion
k_dz
New Contributor
New ContributorInferring RAM with byte-enable from parametrized SystemVerilog
I'm trying to write RAM with byte-enable inputs with parametrizable number of bytes. Templates for RAM with byte-enable in Lite and Standard versions of Quartus assume a certain number of bytes in a ...
Thanks for your design, after investigation, this user guide only can be used of Quartus Pro related devices.(Statix 10, Agilex 7 and etc).
It will not be applicable for Std edition, https://www.intel.com/content/www/us/en/docs/programmable/683082/24-3/ram-with-byte-enable-signals.html#mwh1409959589276__example_SystemVerilog_Simple
In your Quartus, if your right click and insert template, you will see this example in standard edition.
KennyT_altera
Super Contributor
Super ContributorCan you attached your design.qar file for the investigation?
k_dzHere's the project archive containing both the version with for (set as top level, not inferred as RAM) and the one that has been manually unrolled (inferred as RAM). The _w_output archive additionally contains report files.
