Forum Discussion
New ContributorInferring RAM with byte-enable from parametrized SystemVerilog
Thanks for your design, after investigation, this user guide only can be used of Quartus Pro related devices.(Statix 10, Agilex 7 and etc).
It will not be applicable for Std edition, https://www.intel.com/content/www/us/en/docs/programmable/683082/24-3/ram-with-byte-enable-signals.html#mwh1409959589276__example_SystemVerilog_Simple
In your Quartus, if your right click and insert template, you will see this example in standard edition.
New ContributorTo make sure that nothing else affects the synthesis, I'm just setting the file containing only byte_enabled_simple_dual_port_ram module as top level entity and let it use the default parameter values.
Even with HDL_MESSAGE_LEVEL LEVEL3, SYNTH_MESSAGE_LEVEL HIGH and the ramstyle = "M10K" attribute there are no logs regarding ram variable, except for
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "ram" into its bus
I would expect Quartus to at least point why the synthesis attribute is ignored.
