Incremental Place and Route

Hi,

I don't see your problem as that of incremental things. You can design without the need to spy on the fitter decisions at all. The fitter puts stuff as decided by the whole design so things migrate around. Give it freedom. If things are very bad you better see what is going in your design. Are you getting reported skew? then your clocking is to blame I am afraid...

kaz

Thanks Kaz…

I have 3 signal clock form a PLL, whose goes to a mux of 3.

I need that the skew of this signal be 0.

So when I implement the system with out SP (with out SP is the real system) I simulate it and I can calibrate the phase shift of the 3 signal with the PLL, hence, I can compensate the different delay of the mux, hence I can “set” the skew to 0.

So when I’ll test all system in the chip I need use a SP block, because I have 10 binary inputs and I haven’t 10 switches on the board. Using the SP block the fitter change all, hence, the initial calibration on the PLL is useless.

Kaz, can you explain the question please? Because I don’t understand

“Are you getting reported skew?”

My English is not good, so I hope you understand.

So thanks for all.

Ignacio.

Hi,

you should avoid connecting the three clocks to a mux as you will be gating them and causing skew, though this can be done by experienced designers.

I am not clear what is your purpose of getting these three clocks. I thought you will use them for your design work to feed flipflops(registers). You can adjust the phase of each clock in the altpll instantiation(I think that is what you are doing), but this approach is complicated and nonrepeatable and it is better to use one clock for a safe design then control the rate through an enable signal.

By reported skew, I mean the compiler message tells you that there is skew.

kaz

Ok, I understand your idea. But we need the 3 signal clock because is the nucleus of the design, hence I need to know if is possible do the hierarchy compilation with the characteristic that I said in the first message.

Kaz, thanks, really thanks.

Ignacio

Hi,

In that case you can use logiclock or incremental compilation(bottom-up).

There is a lot of info on altera site including a very good video demo.Just make a search for incremental compilation on this site

kaz

--- Quote Start ---

Ok, I understand your idea. But we need the 3 signal clock because is the nucleus of the design, hence I need to know if is possible do the hierarchy compilation with the characteristic that I said in the first message.

Kaz, thanks, really thanks.

Ignacio

--- Quote End ---

Hi Ignacio,

what are you doing with your SP Block ? Where is the block located in your design ?

Which Timing Analyzer did you use and how do you constrain the clock signals ?

I think you want to look at Timing Constraints, specifically TimeQuest. Once you enter timing constraints, the fitter than works to meet those constraints(although in general, there isn't a straightofrward skew constraint). If data comes in and feeds a register clocked by these three clocks, then doing set_input_delay constraints on the input will constrain the datapath in relation to each clock.

Note that it's impossible to have 0ns skew, no matter what technology you have. I'm guessing you want it "as tight as possible". A PLL whose output feeds globals(which it has to) will have very good skew. Probably a hundred picoseconds or so, but timing analysis will tell you more. Once you go to a clock mux out of logic, your skew will jump considerably with careful design, and could get horrible without hand-crafting(i.e. one clock might go through two levels of logic while other clocks only go through one, resulting in a ns of skew). I would look at using the altclkctrl megafunction, although I don't remember if it can mux 3 clocks or only 2. If you can use that, it will get you back to the ideal case.

--- Quote Start ---

I think you want to look at Timing Constraints, specifically TimeQuest. Once you enter timing constraints, the fitter than works to meet those constraints(although in general, there isn't a straightofrward skew constraint). If data comes in and feeds a register clocked by these three clocks, then doing set_input_delay constraints on the input will constrain the datapath in relation to each clock.

Note that it's impossible to have 0ns skew, no matter what technology you have. I'm guessing you want it "as tight as possible". A PLL whose output feeds globals(which it has to) will have very good skew. Probably a hundred picoseconds or so, but timing analysis will tell you more. Once you go to a clock mux out of logic, your skew will jump considerably with careful design, and could get horrible without hand-crafting(i.e. one clock might go through two levels of logic while other clocks only go through one, resulting in a ns of skew). I would look at using the altclkctrl megafunction, although I don't remember if it can mux 3 clocks or only 2. If you can use that, it will get you back to the ideal case.

--- Quote End ---

The altclkcrtl megafunction supports up to 4 inputs. Unfortunately only two could be driven by a pll. It is also not possible to cascade altclkctrl blocks. In my point of view they can not be used here. Maybe somebody has an idea ?

If you really need 3, then you're correct. Another thought is that, depending on the family, PLL's are reconfigurable, so you could reconfigure one of the outputs. This won't allow "instantaneous" change, but might work.

You might want to post what you're doing here for other's input. I have seen designs that absolutely do require clock muxes, but I have seen many cases where users start doing this when there is a much better solution. Also, where does the 0ns(or whatever it is) skew requirement come from?

Well!! Firth of all, I’m sorry I couldn’t replay all the post for two reasons: 1) I didn’t have time and 2) the PC has a little problem.

Kas:

Very thanks, finally I went to the Altera’s page and I found “incremental compilation” I saw a video that explained the problem. The real name of my problem is “Logic lock”

Pletz:

Thanks for your questions.

“What are you doing with your SP Block?”

So when I’ll test all system in the chip I need use a SP block, because I have 10 binary inputs and I haven’t 10 switches on the board.

“Where is the block located in your design?”

In the middle of the chip, more or less.

”Which Timing Analyzer did you use and how do you constrain the clock signals?”

Which? I’m sorry; I don’t understand your question.

I can’t constrain the “clock signals” because when the diferents signals thought the mux of 3 those lose the properties of a signal clock and takes the properties of a common signal. If I don’t wrong the “Timing Analyzer” only function work with cloc signals.

Rysc:

Thank for your advice

I agree with you, but I believe that the “Timing constraints” is only applicable to the clock signal, and my problem is inside mux, and the signals are common, not clocks. I mean the input signal of the mux are clocks but inside are not.

In Clycone II is not possible connect more than 1 output PLL to an “altclkctrl”. If, I don’t remember wrong, the manual of the “altclkctrl megafunction“said this. So this is the reason to use a simple mux of common signal.

Is probably that is not a great idea (use the mux) but for the moment is necessary pass this process to learn.

I'm really grateful for the patience and friendly treatment your have given me.

Really, really thanks.

Ignacio.