Incremental Place and Route

Well!! Firth of all, I’m sorry I couldn’t replay all the post for two reasons: 1) I didn’t have time and 2) the PC has a little problem.

Kas:

Very thanks, finally I went to the Altera’s page and I found “incremental compilation” I saw a video that explained the problem. The real name of my problem is “Logic lock”

Pletz:

Thanks for your questions.

“What are you doing with your SP Block?”

So when I’ll test all system in the chip I need use a SP block, because I have 10 binary inputs and I haven’t 10 switches on the board.

“Where is the block located in your design?”

In the middle of the chip, more or less.

”Which Timing Analyzer did you use and how do you constrain the clock signals?”

Which? I’m sorry; I don’t understand your question.

I can’t constrain the “clock signals” because when the diferents signals thought the mux of 3 those lose the properties of a signal clock and takes the properties of a common signal. If I don’t wrong the “Timing Analyzer” only function work with cloc signals.

Rysc:

Thank for your advice

I agree with you, but I believe that the “Timing constraints” is only applicable to the clock signal, and my problem is inside mux, and the signals are common, not clocks. I mean the input signal of the mux are clocks but inside are not.

In Clycone II is not possible connect more than 1 output PLL to an “altclkctrl”. If, I don’t remember wrong, the manual of the “altclkctrl megafunction“said this. So this is the reason to use a simple mux of common signal.

Is probably that is not a great idea (use the mux) but for the moment is necessary pass this process to learn.

I'm really grateful for the patience and friendly treatment your have given me.

Really, really thanks.

Ignacio.