Incremental Place and Route

Thanks Kaz…

I have 3 signal clock form a PLL, whose goes to a mux of 3.

I need that the skew of this signal be 0.

So when I implement the system with out SP (with out SP is the real system) I simulate it and I can calibrate the phase shift of the 3 signal with the PLL, hence, I can compensate the different delay of the mux, hence I can “set” the skew to 0.

So when I’ll test all system in the chip I need use a SP block, because I have 10 binary inputs and I haven’t 10 switches on the board. Using the SP block the fitter change all, hence, the initial calibration on the PLL is useless.

Kaz, can you explain the question please? Because I don’t understand

“Are you getting reported skew?”

My English is not good, so I hope you understand.

So thanks for all.

Ignacio.