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I think you want to look at Timing Constraints, specifically TimeQuest. Once you enter timing constraints, the fitter than works to meet those constraints(although in general, there isn't a straightofrward skew constraint). If data comes in and feeds a register clocked by these three clocks, then doing set_input_delay constraints on the input will constrain the datapath in relation to each clock.
Note that it's impossible to have 0ns skew, no matter what technology you have. I'm guessing you want it "as tight as possible". A PLL whose output feeds globals(which it has to) will have very good skew. Probably a hundred picoseconds or so, but timing analysis will tell you more. Once you go to a clock mux out of logic, your skew will jump considerably with careful design, and could get horrible without hand-crafting(i.e. one clock might go through two levels of logic while other clocks only go through one, resulting in a ns of skew). I would look at using the altclkctrl megafunction, although I don't remember if it can mux 3 clocks or only 2. If you can use that, it will get you back to the ideal case.
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The altclkcrtl megafunction supports up to 4 inputs. Unfortunately only two could be driven by a pll. It is also not possible to cascade altclkctrl blocks. In my point of view they can not be used here. Maybe somebody has an idea ?
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