Incremental Place and Route

Hi,

you should avoid connecting the three clocks to a mux as you will be gating them and causing skew, though this can be done by experienced designers.

I am not clear what is your purpose of getting these three clocks. I thought you will use them for your design work to feed flipflops(registers). You can adjust the phase of each clock in the altpll instantiation(I think that is what you are doing), but this approach is complicated and nonrepeatable and it is better to use one clock for a safe design then control the rate through an enable signal.

By reported skew, I mean the compiler message tells you that there is skew.

kaz