Incremental compilation for transceiver (HSSI) on Cyclone 10 and Arria 10

On my project, I develop 4 High-Speed Serial Interface (HSSI) which are connected to a FPGA Cyclone 10.

These interfaces are correctly worked, and I want now to fix the implementation on chip to save these design and to reduce compilation time.

My problem is to create a Design Partition with these 4 interfaces. I have to include them into the root partition because I use HSSI transceivers, Intel IP and HSSI-IO. But it seems than root partition cannot be saved and reused in others project (which are use same Cyclone 10 component).

Can you tell me if it is possible and if so, can you explain or redirect me on correct tutorial.

Thanks