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VFlav's avatar
VFlav
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Incremental compilation for transceiver (HSSI) on Cyclone 10 and Arria 10

On my project, I develop 4 High-Speed Serial Interface (HSSI) which are connected to a FPGA Cyclone 10. These interfaces are correctly worked, and I want now to fix the implementation on chip to sav...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

You can use the root partition block-based design reuse flow. It is documented here:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-block-based-design.pdf

And you can find an online training of the flow here:

https://www.intel.com/content/www/us/en/programmable/support/training/course/obbdr100.html

You can use the Fast Preserve option mentioned along with the design reuse flow to speed compile times, but you would need to move to at least 19.3.

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