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CFabr1's avatar
CFabr1
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4 years ago

Implementing old PAL/GAL into HDL

Hi all, I'm porting into Quartus some old schematics for CPLD/FPGA implementation.This old hardware made of TTL gates but there are also some PLDs (GALs and PALs) that I have fusemap of.Some of them...
CFabr1's avatar
CFabr1
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4 years ago

I' trying to translate into Verilog some PAL/GAL devices.I have done this with combinatorial logics but now I'm stuck because I'm dealing with sequential logics.Here's the disassembling of a registered PAL which I want to port in Verilog, you can see there are four regitsered outputs (with clock and OE) 

/** Inputs **/
Pin	2 = i2;
Pin	3 = i3;
Pin	4 = i4;
Pin	5 = i5;
Pin	6 = i6;
Pin	7 = i7;
Pin	8 = i8;
Pin	9 = i9;
Pin	12 = i12;
Pin	13 = i13;
Pin	14 = i14;
Pin	15 = i15;
Pin	16 = i16;
Pin	17 = i17;
Pin	18 = i18;
Pin	19 = i19;

/** Outputs **/
Pin	12 = o12; /**(Combinatorial, Output feedback output, Active low) **/
Pin	13 = o13; /**(Combinatorial, Output feedback output, Active low) **/
Pin	14 = o14; /**(Registered, Output feedback registered, Active low) **/
Pin	15 = o15; /**(Registered, Output feedback registered, Active low) **/
Pin	16 = o16; /**(Registered, Output feedback registered, Active low) **/
Pin	17 = o17; /**(Registered, Output feedback registered, Active low) **/
Pin	18 = o18; /**(Combinatorial, Output feedback output, Active low) **/
Pin	19 = o19; /**(Combinatorial, Output feedback output, Active low) **/

/** Equations **/

!o12 = o13;
o12.oe = vcc;

!o13 = o17 & o18
     # o16 & !o18 & !o19;
o13.oe = vcc;

!o14 .d !i2
      # i2 & !i4 & o14
      # i2 & i4 & !o14;
o14.oe = OE;

!o15 .d !i2
      # i2 & !i4 & !i5 & !o14 & o15
      # i2 & !i4 & i5 & o14 & o15
      # i2 & i4 & !i5 & o14 & o15
      # i2 & i4 & !o14 & !o15
      # i2 & i5 & !o14 & !o15
      # i2 & !i4 & !i5 & o14 & !o15
      # i2 & i4 & i5 & o14 & !o15;
o15.oe = OE;

!o16 .d !i2
      # i2 & !i5 & o15 & o16
      # i2 & !i4 & !i5 & o14 & o16
      # i2 & i5 & !o16
      # i2 & i4 & !o15 & !o16
      # i2 & !o14 & !o15 & !o16;
o16.oe = OE;

!o17 .d !i2
      # i2 & !i3 & i6 & o17
      # i2 & !i3 & o17
      # i2 & !i5 & i6 & o17 & !o19
      # i2 & i3 & i5 & !o17
      # i2 & i3 & !i6 & !o17
      # i2 & i3 & !o17 & o19
      # i2 & !i6 & !o17 & o19;
o17.oe = OE;

!o18 = i3 & o17
     # !i3 & !o17 & o19;
 

!o19 = !i4 & o15 & o16
     # !i4 & o14 & o16;
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi @CFabr1

I don't really get the PAL/GAL devices and its code. Unfortunately, we do not provide support on coding design.

Since you want to convert into sequential logic in Verilog, you may refer to the webpage below on how to do that.

https://www.allaboutcircuits.com/technical-articles/using-verilog-to-describe-a-sequential-circuit/

Or may search for other Verilog website that may helps.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.