CFabr1
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How to set SLOW SLEW RATE in Quartus 17 lite for MAX10 (10M08SCE144C8G)
Hi all, I made my first design with a MAX10 FPGA (part is 10M08SCE144C8G).I'm looking how to change the SLEW RATE under Quartus 17 Lite edition but I cannot see any option under settings menu (like it happens, for example, for MAX7000 devices where I can set a global SLOW SLEW RATE).Is something possible with MAX10 devices and, if yes, how to do it?Thanks in advance.Re: PowerPlay Power Analyzer error
Thanks for reply. I got this output : Info: Running Quartus Prime Assembler Info: Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition Info: Processing started: Sun Dec 31 15:34:08 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off C86S105 -c C86S105 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Warning (292011): Can't generate programming files because you are currently using the Quartus Prime software in Evaluation Mode. Info: Quartus Prime Assembler was successful. 0 errors, 2 warnings Info: Peak virtual memory: 4676 megabytes Info: Processing ended: Sun Dec 31 15:34:11 2023 Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:00 Info: ******************************************************************* Info: Running Quartus Prime PowerPlay Power Analyzer Info: Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition Info: Processing started: Sun Dec 31 15:34:12 2023 Info: Command: quartus_pow --read_settings_files=off --write_settings_files=off C86S105 -c C86S105 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Error (215039): PowerPlay Power Analyzer (quartus_pow) cannot be run. It requires a successful run of the Assembler. The Assembler (quartus_asm) failed or was not run. Error: Quartus Prime PowerPlay Power Analyzer was unsuccessful. 1 error, 1 warning Error: Peak virtual memory: 4670 megabytes Error: Processing ended: Sun Dec 31 15:34:12 2023 Error: Elapsed time: 00:00:00 Error: Total CPU time (on all processors): 00:00:00PowerPlay Power Analyzer error
Hi all, I'm trying to compile a Verilog file under Quartus 17 targeting a Max 10 FPGA (10M08SCE144C8G ) but I get this error all the time : PowerPlay Power Analyzer (quartus_pow) cannot be run. It requires a successful run of the Assembler. The Assembler (quartus_asm) failed or was not run. I set the FLOW_ENABLE_POWER_ANALYZER value to OFF but it did not change anything. Any suggestion?Thanks in advanceRe: LED circuit issue with CPLD and Quartus
I see. Anyway, OPT01 and OPT13 are active LOW signal so, normally they are fixed HIGH and then get asserted to LOW for 2.5us.As well as, LED_CATHODE1 and LED_CATHODE2 shoud be fixed HIGH so that the LEDs will not blink because both anodes are wired to +5V thru 220 Ohm resistors.Therefore, the LEDs should blink only when LED_CATHODE1 and LED_CATHODE2 toggle to LOW.LED circuit issue with CPLD and Quartus
Hi all, I'm trying to implementing under Quartus this simple LED circuit (based on two D flip-flops) using a +5V CPLD (EPM7032) As you can see, there are only three signals inputs to the flip-flops : -LED which can be fixed HIGH or LOW -CLK1 that can be fixed HIGH or asserted (duration is 2.5us) -CLK2 that can be fixed HIGH or asserted (duration is 2.5us) When LED signal is low and CLK1 (or CLK2) is asserted the not negated output goes LOW activating the LED which start to blink (I use LEDs with built-in oscillator). Well, the circuit works well with TTL gates (74LS74 or 74HC74) but when I implement it under Quartus 12.1it does not work well because, when the only CLK2 is asserted and LED2 blinks, also LED1 starts to blink.Here's the Quartus schematics : Which could be the problem?Perhaps I have to turn off some of the Quartus compiler settings (like Auto Global Clock).Thanks in advance for any help or advice.Re: Implementing old PAL/GAL into HDL
I' trying to translate into Verilog some PAL/GAL devices.I have done this with combinatorial logics but now I'm stuck because I'm dealing with sequential logics.Here's the disassembling of a registered PAL which I want to port in Verilog, you can see there are four regitsered outputs (with clock and OE) /** Inputs **/ Pin 2 = i2; Pin 3 = i3; Pin 4 = i4; Pin 5 = i5; Pin 6 = i6; Pin 7 = i7; Pin 8 = i8; Pin 9 = i9; Pin 12 = i12; Pin 13 = i13; Pin 14 = i14; Pin 15 = i15; Pin 16 = i16; Pin 17 = i17; Pin 18 = i18; Pin 19 = i19; /** Outputs **/ Pin 12 = o12; /**(Combinatorial, Output feedback output, Active low) **/ Pin 13 = o13; /**(Combinatorial, Output feedback output, Active low) **/ Pin 14 = o14; /**(Registered, Output feedback registered, Active low) **/ Pin 15 = o15; /**(Registered, Output feedback registered, Active low) **/ Pin 16 = o16; /**(Registered, Output feedback registered, Active low) **/ Pin 17 = o17; /**(Registered, Output feedback registered, Active low) **/ Pin 18 = o18; /**(Combinatorial, Output feedback output, Active low) **/ Pin 19 = o19; /**(Combinatorial, Output feedback output, Active low) **/ /** Equations **/ !o12 = o13; o12.oe = vcc; !o13 = o17 & o18 # o16 & !o18 & !o19; o13.oe = vcc; !o14 .d !i2 # i2 & !i4 & o14 # i2 & i4 & !o14; o14.oe = OE; !o15 .d !i2 # i2 & !i4 & !i5 & !o14 & o15 # i2 & !i4 & i5 & o14 & o15 # i2 & i4 & !i5 & o14 & o15 # i2 & i4 & !o14 & !o15 # i2 & i5 & !o14 & !o15 # i2 & !i4 & !i5 & o14 & !o15 # i2 & i4 & i5 & o14 & !o15; o15.oe = OE; !o16 .d !i2 # i2 & !i5 & o15 & o16 # i2 & !i4 & !i5 & o14 & o16 # i2 & i5 & !o16 # i2 & i4 & !o15 & !o16 # i2 & !o14 & !o15 & !o16; o16.oe = OE; !o17 .d !i2 # i2 & !i3 & i6 & o17 # i2 & !i3 & o17 # i2 & !i5 & i6 & o17 & !o19 # i2 & i3 & i5 & !o17 # i2 & i3 & !i6 & !o17 # i2 & i3 & !o17 & o19 # i2 & !i6 & !o17 & o19; o17.oe = OE; !o18 = i3 & o17 # !i3 & !o17 & o19; !o19 = !i4 & o15 & o16 # !i4 & o14 & o16;Implementing old PAL/GAL into HDL
Hi all, I'm porting into Quartus some old schematics for CPLD/FPGA implementation.This old hardware made of TTL gates but there are also some PLDs (GALs and PALs) that I have fusemap of.Some of them are pure combinatorial logics and perhaps I know how to write a Verilog module (just matter of declaring the I/O and put equations for each output).But others PLDs are registered so they have sequential logics inside (a clock and an output enable pin).So, I'm looking for some help about.Thanks in advance for any tip/suggestion/example.
