Forum Discussion
Occasional ContributorImplementing MIPI DSI-2 on an Agilex 5 device
I'm using the Agilex 5 FPGA E-Series 065B Premium Development Kit.
There isn't much documentation - so I decided to generate the design example and run the simulation in Questa. I generated and ran the "full simulation" design example (MIPI DSI-2 Rx+Tx Simulation) in Quartus 25.1.1. The simulation fails almost immediately the with error "axis_m does not accept back pressure." I'm not sure if we should try to force the "axi4s_vin_in_tready" to always high or if something else in the design should be changed.
So, there doesn't seem to be documentation on how to implement MIPI DSI-2 and the functional simulation doesn't work.
Ultimately, I'm looking for documentation or a functional simulation that shows how to implement MIPI DSI-2 on an Agilex 5 FPGA.
36 Replies
Hi SteveS109 ,
Nice to work with you back, sorry for the delay of response due to the forum migration.
Is it something really important to you ?
The official user guide is coming to out in 1-2 month later. I suggest to refer to that if possible.
Regards,
Wincent
SteveS109Yes - it is very important to the project and cannot wait. Anything you can do to help us is much appreciated.
- SteveS109
The top-level Verilog module ports for the IP are as follows:
I think guidance on how to generate a blackbox IP component for this is what is needed along with top-level connections including what needs to be exported.
// dsi2_dphy_sys.v // Generated using ACDS version 25.3 109 `timescale 1 ps / 1 ps module dsi2_dphy_sys ( input wire dsi2_tx_control_write, // dsi2_tx_control.write input wire dsi2_tx_control_read, // .read input wire [8:0] dsi2_tx_control_address, // .address input wire [31:0] dsi2_tx_control_writedata, // .writedata output wire [31:0] dsi2_tx_control_readdata, // .readdata output wire dsi2_tx_control_readdatavalid, // .readdatavalid output wire dsi2_tx_control_waitrequest, // .waitrequest input wire [3:0] dsi2_tx_control_byteenable, // .byteenable input wire [47:0] dsi2_tx_axi4s_vid_in_tdata, // dsi2_tx_axi4s_vid_in.tdata input wire dsi2_tx_axi4s_vid_in_tvalid, // .tvalid output wire dsi2_tx_axi4s_vid_in_tready, // .tready input wire dsi2_tx_axi4s_vid_in_tlast, // .tlast input wire [5:0] dsi2_tx_axi4s_vid_in_tuser, // .tuser input wire dsi2_tx_frame_start_conduit, // dsi2_tx_frame_start.conduit output wire dsi2_tx_axi4s_clk_bridge_out_clk_clk, // dsi2_tx_axi4s_clk_bridge_out_clk.clk output wire dsi2_tx_axi4s_reset_bridge_out_reset_reset, // dsi2_tx_axi4s_reset_bridge_out_reset.reset input wire mipi_dphy_rzq_rzq, // mipi_dphy_rzq.rzq input wire mipi_dphy_ref_clk_0_clk, // mipi_dphy_ref_clk_0.clk input wire [11:0] mipi_dphy_axi_lite_awaddr, // mipi_dphy_axi_lite.awaddr input wire mipi_dphy_axi_lite_awvalid, // .awvalid output wire mipi_dphy_axi_lite_awready, // .awready input wire [31:0] mipi_dphy_axi_lite_wdata, // .wdata input wire [3:0] mipi_dphy_axi_lite_wstrb, // .wstrb input wire mipi_dphy_axi_lite_wvalid, // .wvalid output wire mipi_dphy_axi_lite_wready, // .wready output wire [1:0] mipi_dphy_axi_lite_bresp, // .bresp output wire mipi_dphy_axi_lite_bvalid, // .bvalid input wire mipi_dphy_axi_lite_bready, // .bready input wire [11:0] mipi_dphy_axi_lite_araddr, // .araddr input wire mipi_dphy_axi_lite_arvalid, // .arvalid output wire mipi_dphy_axi_lite_arready, // .arready output wire [31:0] mipi_dphy_axi_lite_rdata, // .rdata output wire [1:0] mipi_dphy_axi_lite_rresp, // .rresp output wire mipi_dphy_axi_lite_rvalid, // .rvalid input wire mipi_dphy_axi_lite_rready, // .rready input wire [2:0] mipi_dphy_axi_lite_arprot, // .arprot input wire [2:0] mipi_dphy_axi_lite_awprot, // .awprot output wire mipi_dphy_reg_bus_reg_wr_en_o, // mipi_dphy_reg_bus.reg_wr_en_o output wire mipi_dphy_reg_bus_reg_rd_en_o, // .reg_rd_en_o output wire [10:0] mipi_dphy_reg_bus_reg_raddr_o, // .reg_raddr_o output wire [10:0] mipi_dphy_reg_bus_reg_waddr_o, // .reg_waddr_o output wire [3:0] mipi_dphy_reg_bus_reg_be_o, // .reg_be_o output wire [31:0] mipi_dphy_reg_bus_reg_din_o, // .reg_din_o input wire [31:0] mipi_dphy_reg_bus_reg_dout_i, // .reg_dout_i output wire mipi_dphy_LINK1_link_core_srst_reset_n, // mipi_dphy_LINK1_link_core_srst.reset_n output wire [1:0] mipi_dphy_LINK1_dphy_io_dphy_link_dp, // mipi_dphy_LINK1_dphy_io.dphy_link_dp output wire [1:0] mipi_dphy_LINK1_dphy_io_dphy_link_dn, // .dphy_link_dn output wire mipi_dphy_LINK1_dphy_io_dphy_link_cp, // .dphy_link_cp output wire mipi_dphy_LINK1_dphy_io_dphy_link_cn, // .dphy_link_cn output wire mipi_dphy_link1_link_core_clock_bridge_out_clk_clk, // mipi_dphy_link1_link_core_clock_bridge_out_clk.clk output wire mipi_dphy_link1_link_core_reset_bridge_out_reset_reset // mipi_dphy_link1_link_core_reset_bridge_out_reset.reset );
