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SteveS109's avatar
SteveS109
Icon for Occasional Contributor rankOccasional Contributor
3 months ago

Implementing MIPI DSI-2 on an Agilex 5 device

I'm using the Agilex 5 FPGA E-Series 065B Premium Development Kit. There isn't much documentation - so I decided to generate the design example and run the simulation in Questa. I generated and ran ...
Anonymous's avatar
Anonymous
3 months ago

Hi SteveS109​ ,

Nice to work with you back, sorry for the delay of response due to the forum migration.
Is it something really important to you ?
The official user guide is coming to out in 1-2 month later. I suggest to refer to that if possible.

Regards,
Wincent


  • SteveS109's avatar
    SteveS109
    Icon for Occasional Contributor rankOccasional Contributor
    3 months ago

    Yes - it is very important to the project and cannot wait.  Anything you can do to help us is much appreciated.

    • Anonymous's avatar
      Anonymous
      3 months ago

      Hi Steve,

      Do you run "analysis and synthesis(at least)" or full compilation after you generate the design ?

      Regards,
      Wincent

      • Anonymous's avatar
        Anonymous
        3 months ago

        Hi SteveS109​ ,

        Please refer to my .ip setting below. I try it and it is success.

        Please ensure that you had run the "Analysis & Synthesis" before running the simulation
        Locate your directory under ../x/../ed_sim/sim/mentor

        1. vsim &
        2. do msim_setup.tcl
        3. ld_debug - add wave from the left side 
        4. run -all

        I can get my simulation PASS

        Let me know if you still unable to do it.

        Regards,
        Wincent