Forum Discussion
Yes - it is very important to the project and cannot wait. Anything you can do to help us is much appreciated.
Hi Steve,
Do you run "analysis and synthesis(at least)" or full compilation after you generate the design ?
Regards,
Wincent
- Anonymous3 months ago
Hi SteveS109 ,
Please refer to my .ip setting below. I try it and it is success.Please ensure that you had run the "Analysis & Synthesis" before running the simulation
Locate your directory under ../x/../ed_sim/sim/mentor- vsim &
- do msim_setup.tcl
- ld_debug - add wave from the left side
- run -all
I can get my simulation PASS
Let me know if you still unable to do it.
Regards,
Wincent- SteveS1093 months ago
Occasional Contributor
The simulation with default video timing looked great to me - it looks very solid. No issue with the simulation - it looks much better in the design example from Quartus 25.3. It is a very long sim so I didn't run to completion - I stopped it after about 1/2 hour but it looks very good.
My remaining concern is about generating video timing IP parameters for an 800x600 display. If you have any informal equations to copy & paste into the forum - that would be great. As I mentioned, the params generated by chatGPT were not acceptable to Quartus 25.3 when attempting to generate the IP design example.
You didn't explicitly say that the parameters in your screen shots above will work for an SVGA display - but I can try it. I will use what you provided to proceed through the whole build process.
- SteveS1093 months ago
Occasional Contributor
FYI/for what it's worth - simulating the MIPI DSI-2 design example from Q25.3 also passed for me.