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EGrom1's avatar
EGrom1
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5 years ago

I need to know how to promote signals to use the global or regional clock network for routing and also how to ensure signals are **not** using these resources for routing

1) Background: From the design assistant report there are a couple of signals listed where I really think signal skew needs to be reduced as much as possible but most of them would not profit. 2) S...
EGrom1's avatar
EGrom1
Icon for New Contributor rankNew Contributor
5 years ago

OK, I found out on my own.

  1. you cannot turn this off for individual signals in the source code
  2. turn off automatic global assignment on the project level (in the .qsf file or in the assignment editor). -> set_instance_assignment -name AUTO_GLOBAL_CLOCK OFF -to *
  3. now no signal is automatically promoted and you can set specific signals to use global routing resources. This can be done in the assignment editor as described above or with attributes in the source code -> (* altera_attribute = "-name GLOBAL_SIGNAL GLOBAL_CLOCK" *)

More details about Verilog HDL attributes can be found here: https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_attribute.htm