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EGrom1's avatar
EGrom1
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5 years ago

I need to know how to promote signals to use the global or regional clock network for routing and also how to ensure signals are **not** using these resources for routing

1) Background: From the design assistant report there are a couple of signals listed where I really think signal skew needs to be reduced as much as possible but most of them would not profit. 2) S...
EGrom1's avatar
EGrom1
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5 years ago

Thank you KhaiY, that helped. Sometimes Quartus is a bit of a maze ~:o)

Followup question: is it possible to do this in Verilog source code, similar to setting I/O pin logic levels and pin assignments?

Elmar