I have a problem in importing FFT IP Core into SOPC Builder

To stop SOPCB from analyzing the IP library, you may need to write a simple wrapper HDL.

Or if you instantiate FFT IP in verilog, component editor may accept the top verilog code as is.

As a matter of fact, since FFT IP has non-pure Avalon-ST signals, ex. multiple output data buses for a single sop/eop pair, you have to write a wrapper code to connect with other SOPCB components such as SGDMA...

Finally! I have been looking for some reference to how to connect the FFT IP core properly to the NIOS II everywhere!!! I realize that since this thread is many months old, I probably won't get a response. But I can hope (and post elsewhere).

So my question is, what is the best way to interface the FFT module with a NIOS II? I have tried all sorts of stuff. I finally stumbled on a wrapped module for the FFT which turns the real/imag inputs and outputs into 32 bit data buses, and then put this module into the SOPC builder. I made the extra stuff like the inverse signal and the reset line be exported signals so I could just hook those up at the top level, and I am ignoring the exponent line cause I had no idea how to deal with that. Now I have this in the SOPC but no clue how to hook it up. I tried an on chip FIFO memory and auto generated the adapters, but I couldn't get the thing working. How does one do a standard Avalon-ST streaming interface using SOPC and NIOS II IDE software? It seems very very complicated. Is there a way to get NIOS II IDE to generate the FFT using the C++ files and C-to-Hardware accelerator?? Please help. I have basically read every piece of relevant Altera documentation and looked at many examples, but nothing specifically touches on this.

~Parker:(

Dear Parker

i have made my graduation project in the implementation of an SDR Tranciever using multiprocessors, i have made it using 6 Nios Processors and and some hardware accelerators like FFT, IFFT and Viterbi decoder, i have managed to connect all these stuff to the processors using FIFOs, i have attached the full block diagram of the Tranciever, if you still do need any help in theses things just mail me at alhassan_moh@aucegypt.edu as i am now very famillier with altera FPGA design tools used to deal with Nios processors , best of luck

yours

Alhassan Mohamed Fattin

Teaching Assistant

Faculty of Engineering

Cairo University & American University in Cairo

Hello

I understand that this is old thread, but I have the same problem and don't know how to solve it. This is my error:

"Error: Error (10481): VHDL Use Clause error at FFTTransform.vhd(33): design library "fft_lib" does not contain primary unit "fft_pack_fft_72" File: C:/Elena/QuartusProjects/FFTTransform/FFTTransform.vhd Line: 33

Error: Error (10800): VHDL error at FFTTransform.vhd(33): selected name in use clause is not an expanded name File: C:/Elena/QuartusProjects/FFTTransform/FFTTransform.vhd Line: 33"

Could anyone help me?

Regards, Elena

Hi I'm using Quartus II 9.0 and I'm starting to integrate an instance of the FFT Megafunction into SOPC-Builder System right now. The problem of the missing unit (fft_pack_fft_90) also occurs in Quartus II 9.0, but it can be solved.

First add the VHDL file of the FFT Megafunction instance in the "new component editor". As a result the error message occurs in dicating the missing unit fft_pack_fft_90.vhd within the fft_lib.

Second add the VHDL file with the name of the missing unit (fft_pack_fft_90.vhd), located in ..\altera\90\ip\altera\fft\lib\.

Third press the button Re-analyze. READY

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Hi I'm using Quartus II 9.0 and I'm starting to integrate an instance of the FFT Megafunction into SOPC-Builder System right now. The problem of the missing unit (fft_pack_fft_90) also occurs in Quartus II 9.0, but it can be solved.

First add the VHDL file of the FFT Megafunction instance in the "new component editor". As a result the error message occurs in dicating the missing unit fft_pack_fft_90.vhd within the fft_lib.

Second add the VHDL file with the name of the missing unit (fft_pack_fft_90.vhd), located in ..\altera\90\ip\altera\fft\lib\.

Third press the button Re-analyze. READY

--- Quote End ---

Your method works well. Thanks