Forum Discussion
Altera_Forum
Honored Contributor
17 years agoDear Parker
i have made my graduation project in the implementation of an SDR Tranciever using multiprocessors, i have made it using 6 Nios Processors and and some hardware accelerators like FFT, IFFT and Viterbi decoder, i have managed to connect all these stuff to the processors using FIFOs, i have attached the full block diagram of the Tranciever, if you still do need any help in theses things just mail me at alhassan_moh@aucegypt.edu as i am now very famillier with altera FPGA design tools used to deal with Nios processors , best of luck yours Alhassan Mohamed Fattin Teaching Assistant Faculty of Engineering Cairo University & American University in Cairo