I have a problem in importing FFT IP Core into SOPC Builder

To stop SOPCB from analyzing the IP library, you may need to write a simple wrapper HDL.

Or if you instantiate FFT IP in verilog, component editor may accept the top verilog code as is.

As a matter of fact, since FFT IP has non-pure Avalon-ST signals, ex. multiple output data buses for a single sop/eop pair, you have to write a wrapper code to connect with other SOPCB components such as SGDMA...