I can't compile my code to generate a PWM signal

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Hi everyone

When I compile my code a problem with the syntax appears and I can't find the problem. The objective of my code is generate a PWM signal:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;
entity pwm_generator is
port(    a, b:        in bit_vector (31 downto 0);
        c:            out bit);
end pwm_generator; 
--The input 'a' means the frequency, of signal pwm, in binary. For example 1234Hz is 00000000000000000000010011010010Hz
--The input 'b' means the duty cicle in binary. For example 27% is 00000000000000000000000000011011%
--The output 'c' means the output of pwm signal.
architecture logical of pwm_generator is
variable t, e, a1, b1, f: integer;
--The variable 't' means the period (in seconds) of pwm signal.
--The variable 'e' means the time (in seconds) of the high level ('1') of the pwm signal.
--The variable 'a1' means the decimal representation of the input 'a'.
--The variable 'b1' means the decimal representation of the input 'b'.
--The variable 'f' means the time (in seconds) of the low level ('0') of the pwm signal.
    begin
        a1 := to_integer(unsigned(to_stdlogicvector(a)));
        b1 := to_integer(unsigned(to_stdlogicvector(b)));
        t := 1/a1;
        e := t*b1;
        f := t-e;
        process
            begin
                L1: loop
                    c <= '1';
                    wait for e;
                    c <= '0';
                    wait for f;
                end loop;
        end process;
end logical;

The error is { Error (10500): VHDL syntax error at test_language_vhdl.vhd(27) near text ":="; expecting "(", or "'", or "." }

Thanks in advance.

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declare your variables after process. I am not sure if your code is synthesisable due to wait for.

I declared the variables after "process" and now another error appears, involving the division operator. My new code is:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
entity pwm_generator is
port(	a, b:		in bit_vector (31 downto 0);
		c:			out bit);
end pwm_generator; 
--The input 'a' means the frequency, of signal pwm, in binary. For example 1234Hz is 00000000000000000000010011010010Hz
--The input 'b' means the duty cicle in binary. For example 27% is 00000000000000000000000000011011%
--The output 'c' means the output of pwm signal.
architecture logical of pwm_generator is
begin
	process
	
	variable a1, b1: integer;
	variable t, e, f, b2: real;
		
	--The variable 't' means the period (in seconds) of pwm signal.
	--The variable 'e' means the time (in seconds) of the high level ('1') of the pwm signal.
	--The variable 'a1' means the decimal representation of the input 'a'.
	--The variable 'b1' means the decimal representation of the input 'b'.
	--The variable 'f' means the time (in seconds) of the low level ('0') of the pwm signal.
	--The variable 'b2' means the percentage in decimal of 'b1'.
	begin
		a1 := to_integer(unsigned(to_stdlogicvector(a)));
		b1 := to_integer(unsigned(to_stdlogicvector(b)));
		b2 := b1/100;
		t := 1/a1;
		e := t*b2;
		f := t-e;
		
			L1: loop
					c <= '1';
					wait for e;
					c <= '0';
					wait for f;
			end loop;
			
	end process;
	
end logical;

The error is: { Error (10327): VHDL error at teste_linguagem_vhdl.vhd(33): can't determine definition of operator ""/"" -- found 0 possible definitions

}.

About the "wait for" if don't work I'll change my idea.

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I declared the variables after "process" and now another error appears, involving the division operator. My new code is:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
entity pwm_generator is
port(    a, b:        in bit_vector (31 downto 0);
        c:            out bit);
end pwm_generator; 
--The input 'a' means the frequency, of signal pwm, in binary. For example 1234Hz is 00000000000000000000010011010010Hz
--The input 'b' means the duty cicle in binary. For example 27% is 00000000000000000000000000011011%
--The output 'c' means the output of pwm signal.
architecture logical of pwm_generator is
begin
    process
    
    variable a1, b1: integer;
    variable t, e, f, b2: real;
        
    --The variable 't' means the period (in seconds) of pwm signal.
    --The variable 'e' means the time (in seconds) of the high level ('1') of the pwm signal.
    --The variable 'a1' means the decimal representation of the input 'a'.
    --The variable 'b1' means the decimal representation of the input 'b'.
    --The variable 'f' means the time (in seconds) of the low level ('0') of the pwm signal.
    --The variable 'b2' means the percentage in decimal of 'b1'.
    begin
        a1 := to_integer(unsigned(to_stdlogicvector(a)));
        b1 := to_integer(unsigned(to_stdlogicvector(b)));
        b2 := b1/100;
        t := 1/a1;
        e := t*b2;
        f := t-e;
        
            L1: loop
                    c <= '1';
                    wait for e;
                    c <= '0';
                    wait for f;
            end loop;
            
    end process;
    
end logical;

The error is: { Error (10327): VHDL error at teste_linguagem_vhdl.vhd(33): can't determine definition of operator ""/"" -- found 0 possible definitions

}.

About the "wait for" if don't work I'll change my idea.

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just comment out t:1/a1 as it is not doing anything. After all / is not supported for synthesis as far as I know

Frankly I don't understand what you are aiming at.

also avoid mixing of libraries, just use numeric_std instead of signed/unsigned

edit: sorry about t, it is used later but you can't use / for synthesis

I suggest the following:

set your inputs as follows:

a: in std_logic_vector(15 downto 0);

b: in std_logic_vector(7 downto 0);

clkin: in std_logic;

clkout: out std_logic

(a) to be your clkout period in clk samples (not absolute time and not frequency)

(b) is duty cycle but scaled by 128/100(to avoid division)

compute (b1) from (a) & (b) in logic as follows:

in logic multiply (b) by (a) then discard 7 bits b1 = a*b/128 (e.g. for 27% duty cycle b1 = a*35/128)

run a counter on clk starting from zero and increment by 1 till a value equal to (a-1) and back.

finally decide clkout logic: if count = (b1-1) clkout to be high and if count = (a-1) clkout to be low (or the reverse).