I can't compile my code to generate a PWM signal

I declared the variables after "process" and now another error appears, involving the division operator. My new code is:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
entity pwm_generator is
port(	a, b:		in bit_vector (31 downto 0);
		c:			out bit);
end pwm_generator; 
--The input 'a' means the frequency, of signal pwm, in binary. For example 1234Hz is 00000000000000000000010011010010Hz
--The input 'b' means the duty cicle in binary. For example 27% is 00000000000000000000000000011011%
--The output 'c' means the output of pwm signal.
architecture logical of pwm_generator is
begin
	process
	
	variable a1, b1: integer;
	variable t, e, f, b2: real;
		
	--The variable 't' means the period (in seconds) of pwm signal.
	--The variable 'e' means the time (in seconds) of the high level ('1') of the pwm signal.
	--The variable 'a1' means the decimal representation of the input 'a'.
	--The variable 'b1' means the decimal representation of the input 'b'.
	--The variable 'f' means the time (in seconds) of the low level ('0') of the pwm signal.
	--The variable 'b2' means the percentage in decimal of 'b1'.
	begin
		a1 := to_integer(unsigned(to_stdlogicvector(a)));
		b1 := to_integer(unsigned(to_stdlogicvector(b)));
		b2 := b1/100;
		t := 1/a1;
		e := t*b2;
		f := t-e;
		
			L1: loop
					c <= '1';
					wait for e;
					c <= '0';
					wait for f;
			end loop;
			
	end process;
	
end logical;

The error is: { Error (10327): VHDL error at teste_linguagem_vhdl.vhd(33): can't determine definition of operator ""/"" -- found 0 possible definitions

}.

About the "wait for" if don't work I'll change my idea.