I can't compile my code to generate a PWM signal

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Hi everyone

When I compile my code a problem with the syntax appears and I can't find the problem. The objective of my code is generate a PWM signal:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;
entity pwm_generator is
port(    a, b:        in bit_vector (31 downto 0);
        c:            out bit);
end pwm_generator; 
--The input 'a' means the frequency, of signal pwm, in binary. For example 1234Hz is 00000000000000000000010011010010Hz
--The input 'b' means the duty cicle in binary. For example 27% is 00000000000000000000000000011011%
--The output 'c' means the output of pwm signal.
architecture logical of pwm_generator is
variable t, e, a1, b1, f: integer;
--The variable 't' means the period (in seconds) of pwm signal.
--The variable 'e' means the time (in seconds) of the high level ('1') of the pwm signal.
--The variable 'a1' means the decimal representation of the input 'a'.
--The variable 'b1' means the decimal representation of the input 'b'.
--The variable 'f' means the time (in seconds) of the low level ('0') of the pwm signal.
    begin
        a1 := to_integer(unsigned(to_stdlogicvector(a)));
        b1 := to_integer(unsigned(to_stdlogicvector(b)));
        t := 1/a1;
        e := t*b1;
        f := t-e;
        process
            begin
                L1: loop
                    c <= '1';
                    wait for e;
                    c <= '0';
                    wait for f;
                end loop;
        end process;
end logical;

The error is { Error (10500): VHDL syntax error at test_language_vhdl.vhd(27) near text ":="; expecting "(", or "'", or "." }

Thanks in advance.

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declare your variables after process. I am not sure if your code is synthesisable due to wait for.