I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi Albert,

In the Intel Quartus Prime software, you have to add the logic design files that contain the logic that implements your design into the Project. The source file can be in HDL(.v/.vhd/.sv), Verilog Quartus Mapping (.vqm) design files and Platform Designer (Standard) system (.qsys). It this case, it is not possible to instantiate BRAM_16x1S without the source file that describes how BRAM_16x1S works in the design.

To add the files into the Project

1) Click on Project > Add/Remove Files in Project

2) Click on ... icon to add the files

3) Ok

Thanks.

Best regards,

KhaiY