I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi KhaiY, that is the problem, why it probably isn't working in Quartus II. But this file as it is, works splendidly in Xilinx ISE 14.6 without any problem! That is why I asked this question. I just noticed that it only works in Xilinx ISE 14.6 when a higher type FPGA is chosen. Earlier Xilinx FPGA's probably were unable to work as BRAM configurated FPGA's.

Because a Xilinx Spartan 3E failed to compile this BRAM file that works splendidly on a Xilinx Zynq XA 7z010 FPGA as it was given in the above mentioned BRAM_16x2 vhdl file from the book : PLD BASED DESIGN WITH VHDL by Vaibbhav Taraate.

I know too little yet about the Quartus II and Xilinx ISE programs to know why the file creates problems in Quartus II. But I guess it has to do with what version of program is used.

Thanks!

Albert.