I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

In addition to previous comment I like to mention that the RTL viewer error in the Mux 4to2 encoder probably is at the Equal0 symbol that has 4'h1 for marking which if I'm not mistaken should be 4'h8 instead? I do not know if these errors are patched after the upgrade is done but sadly the upgrade can't be downloaded without the already installed Quartus 13.1 edition connected to the internet. Why I need an offline upgrade

package to install over my not internet connected Quartus installed computer.

Hi,

Please upgrade the design to the latest version of the Intel Quartus Prime Lite edition software as some of the bugs in the older version are fixed in the later version. You may download the latest software using another internet connected PC and install in your current PC.

Thanks.

Best regards,

KhaiY

Thank you KhaiY, but I can't do that because I need my Quartus II 13.1 version because of still supporting the older Spartan 3 FPGA's. Yesterday I was not being able to download the upgrade files for version 13.1 because they seemed hidden somehow.

But today the download links to both upgrade files (930MB and 407.8MB) worked, so it seems that the upgrade is going to work now. And I hope that it will remove the RTL schematic bug where "1000" is seen as 4'h1 instead of 4'h8 in the Equation symbols.

Thanks!

PS: after upgrade and a first test the error is fixed GREAT!

I however still found a strange RTL result in an Excess3 converter.

Above

Above the strange 16bit results in the 4 muxes in the RTL viewer Excess3 converter window. In the program code 4 bits wide is the highest declared. What is wrong here? Is it another bug in the RTL viewer, or has it to do with taking the negative 2 complement and adding 9's to get the positive Excess3 equivalent value?

Hi,

Could you provide the design.qar for investigation? I can help to test on my side.

Thanks.

Best regards,

KhaiY

Hi,

You may create the design.qar by clicking on Project > Archive Project > Archive

Thanks.

Best regards,

KhaiY

Hi,

Upon checking, the schematic in RTL VIewer with Synthesis rtl dump file are the same, there is no mismatch in the result. Have you tried simulate the design to check the functionality?

Thanks.

Best regards,

KhaiY

Hi KhaiY, this problem was already solved in the past by upgrading my buggy 13.1 Quartus II version. I did however leave another answer on the Forum that was another problem. I add it below. And I think it is caused by differences in the FPGA structures and/or differences between the VHDL designers from Quartus and Xilinx:

• Quartus II 13.1 (upgraded) fails terribly where Xilinx produces perfect RTL schematics from the same VHDL code! And I already upgraded Quartus to get rid of the wrong terrible bugs that showed in its RTL results. And the Intel site gave none help, no support to ask a question by sending a simple email sadly!
• See next code that after days of wasted checking keeps failing in Quartus but works great as it is in Xilinx ISE 14.6!
• HELP !!! QUARTUS II Web free version 13.1 (32-bit) for Windows 7 fails many times to compile a perfectly good VHDL example code!
• Those examples tried never work in Quartus but the same files
• WORK PERFECTLY in Xilinx ISE version 14.6 !!! (on a Windows XP laptop).
• See following VHDL code below of an UpCounter that never works in Quartus II for some reason but works great in Xilinx ISE producing a decent and correct RTL schematic!
• ----------------
• -- Engineer: Albert van Bemmelen
• -- Create Date: 15:46:31 05/09/2020
• -- Module Name: UpCounter - Behavioral
• -- Upcounter Vahid book
• library ieee;
• use ieee.std_logic_1164.all;
• entity UpCounter is
• port ( clk: in std_logic;
• cnt: in std_logic;
• C: out std_logic_vector(3 downto 0);
• tc: out std_logic);
• end UpCounter;
• architecture structure of UpCounter is
• component Reg4
• port ( I: in std_logic_vector(3 downto 0);
• Q: out std_logic_vector(3 downto 0);
• clk, ld: in std_logic);
• end component;
• component Inc4
• port ( a: in std_logic_vector(3 downto 0);
• s: out std_logic_vector(3 downto 0));
• end component;
• component And_4
• port ( w,x,y,z: in std_logic;
• F: out std_logic);
• end component;
• signal tempC: std_logic_vector (3 downto 0);
• signal incC: std_logic_vector(3 downto 0);
• begin
• Reg4_1: Reg4 port map(incC, tempC, clk, cnt);
• Inc4_1: Inc4 port map(tempC, incC);
• And_4_1: And_4 port map(tempC(3),tempC(2),tempC(1),tempC(0), tc);
• outputC: process(tempC)
• begin
• C <= tempC;
• end process;
• end structure;
• I am trying to understand why Quartus makes a problem of good VHDL code where it shouldn't be!!
• Any help is greatly appreciated!
• Albert van Bemmelen
• Weert The Netherlands.

Hi,

Have you tried to compile in the latest version of the software, which is 19.1 as some of the bugs in the older version were fixed in the newer version?

Thanks.

Best regards,

KhaiY

No sadly for not being able to install the 64 bit versions on old laptops or old windows 7 and earlier versions. And because I need to work with my Digilent Spartan 3E experimenter's board. And I use my only online Windows 10 laptop for safe online action only.