I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi KhaiY, this problem was already solved in the past by upgrading my buggy 13.1 Quartus II version. I did however leave another answer on the Forum that was another problem. I add it below. And I think it is caused by differences in the FPGA structures and/or differences between the VHDL designers from Quartus and Xilinx:

• Quartus II 13.1 (upgraded) fails terribly where Xilinx produces perfect RTL schematics from the same VHDL code! And I already upgraded Quartus to get rid of the wrong terrible bugs that showed in its RTL results. And the Intel site gave none help, no support to ask a question by sending a simple email sadly!
• See next code that after days of wasted checking keeps failing in Quartus but works great as it is in Xilinx ISE 14.6!
• HELP !!! QUARTUS II Web free version 13.1 (32-bit) for Windows 7 fails many times to compile a perfectly good VHDL example code!
• Those examples tried never work in Quartus but the same files
• WORK PERFECTLY in Xilinx ISE version 14.6 !!! (on a Windows XP laptop).
• See following VHDL code below of an UpCounter that never works in Quartus II for some reason but works great in Xilinx ISE producing a decent and correct RTL schematic!
• ----------------
• -- Engineer: Albert van Bemmelen
• -- Create Date: 15:46:31 05/09/2020
• -- Module Name: UpCounter - Behavioral
• -- Upcounter Vahid book
• library ieee;
• use ieee.std_logic_1164.all;
• entity UpCounter is
• port ( clk: in std_logic;
• cnt: in std_logic;
• C: out std_logic_vector(3 downto 0);
• tc: out std_logic);
• end UpCounter;
• architecture structure of UpCounter is
• component Reg4
• port ( I: in std_logic_vector(3 downto 0);
• Q: out std_logic_vector(3 downto 0);
• clk, ld: in std_logic);
• end component;
• component Inc4
• port ( a: in std_logic_vector(3 downto 0);
• s: out std_logic_vector(3 downto 0));
• end component;
• component And_4
• port ( w,x,y,z: in std_logic;
• F: out std_logic);
• end component;
• signal tempC: std_logic_vector (3 downto 0);
• signal incC: std_logic_vector(3 downto 0);
• begin
• Reg4_1: Reg4 port map(incC, tempC, clk, cnt);
• Inc4_1: Inc4 port map(tempC, incC);
• And_4_1: And_4 port map(tempC(3),tempC(2),tempC(1),tempC(0), tc);
• outputC: process(tempC)
• begin
• C <= tempC;
• end process;
• end structure;
• I am trying to understand why Quartus makes a problem of good VHDL code where it shouldn't be!!
• Any help is greatly appreciated!
• Albert van Bemmelen
• Weert The Netherlands.