Hyper-Retiming, How to disable it in the .qsf?

Hi Alex,

You can disable retiming using this command: https://www.intel.com/content/www/us/en/docs/programmable/683236/22-1/allow-register-retiming.html

Regards,

Nurina

Hi Alex,

I don't think you can entirely skip the Retime stage, the big selling point of a HyperFlex device is the ability to improve timing with the Retime stage. How much time is used for Retime stage?

You can try other steps to reduce Retime compilation time/effort.

• Choose Compiler Optimization Modes: https://www.intel.com/content/www/us/en/docs/programmable/683236/22-1/compiler-optimization-modes.html
• Disable all retime/retiming related settings in Advanced Fitter Settings. Go to Assignments>Settings>Compiler Settings>Advanced Settings (Fitter)
• Disable Design Assistant Rule in Retime stage (if any): https://www.intel.com/content/www/us/en/docs/programmable/683236/21-3/hyperflex-settings.html
• Disable Intermediate Fitter Snapshots for Retime stage (if any): https://www.intel.com/content/www/us/en/docs/programmable/683236/21-3/enable-intermediate-fitter-snapshots.html

Regards,

Nurina

For one project it took 8 min,

for the other project it took 38 min (still unable to optimize the design, so it is maybe a big selling point, but if not applicable to our design ...).

I will try the other options you provided.

When I use aggressive compile time, Hyper-retimer runs as long as with balanced setting.

Enable intermediate fitter snapshot was already unticked.

Would it be possible to add an option in future release of Quartus to be able to turn it off?

I use Synplify for the synthesis, I can use retiming in that tool (yes I know that Quartus has a place and route overview that can lead to a better retime too over synplify).

Retiming normally does not take very long because it is using the post-fit netlist and doesn't make changes to that netlist. All it does is make decisions about moving registers from LABs to hyper-register locations.

Retiming in a different tool would be based on the synthesis netlist. That's a different type of retiming from the hyper-retiming performed on the post-fit netlist by Quartus.

Are you saying that just the hyper-retiming stage itself took 38 minutes or the overall compile was that long?

If just the hyper-retimer is taking that long, then maybe there is some other related setting enabled, or maybe a fast forward compile is being run automatically or something.

Hi Alex,

I could certainly make a request for an option to disable it.

I need some confidential details from you, I will drop you an email.

Does above comment help to improve compile time by the way?

Regards,

Nurina

Hi,

Yes, the retime stage compilation time would definitely take longer with a bigger project or if the tool is putting more effort in meeting timing.

Similarly all the other stages take longer time with a bigger project.

Regards,

Nurina

Hi Alex,

May I know if there is any update on this issue?

Hello,

I can request for an option to disable it.

Apologies as it turns out I didn't send you that email previously mentioned.

Dropping you one right now so we can continue this case through email.

Regards,

Nurina

Hello Alex,

My apologies, this qsf setting is intended for Stratix 10 GX 10M, I can see that you are using Stratix 10 SX.

Let me check with internal team on the expectation of this qsf setting.

On the other hand, we strongly advise using Stratix 10 GX 10M for ASIC prototyping projects as this device is intended for ASIC prototyping and offers high capacity & large connectivity with the DIB IP and other features that makes it perfect for ASIC Prototyping.

More information regarding the Stratix 10 GX 10M here: https://www.intel.com/content/www/us/en/products/sku/210290/intel-stratix-10-gx-10m-fpga/specifications.html

DIB IP: https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/about-the-dib-fpga-ip-user-guide.html

Regards,

Nurina