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AEsqu's avatar
AEsqu
Icon for Contributor rankContributor
2 years ago

Hyper-Retiming, How to disable it in the .qsf?

Hyper-Retiming, How to disable it in the .qsf? I'm asking because Quartus is not able to apply it on my design, hence I want to skip it to save run time (stratix 10, Quartus 21.1). Messages from ...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello Alex,


My apologies, this qsf setting is intended for Stratix 10 GX 10M, I can see that you are using Stratix 10 SX.

Let me check with internal team on the expectation of this qsf setting.


On the other hand, we strongly advise using Stratix 10 GX 10M for ASIC prototyping projects as this device is intended for ASIC prototyping and offers high capacity & large connectivity with the DIB IP and other features that makes it perfect for ASIC Prototyping.

More information regarding the Stratix 10 GX 10M here: https://www.intel.com/content/www/us/en/products/sku/210290/intel-stratix-10-gx-10m-fpga/specifications.html

DIB IP: https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/about-the-dib-fpga-ip-user-guide.html


Regards,

Nurina


AEsqu's avatar
AEsqu
Icon for Contributor rankContributor
2 years ago

Ok let me know if you have another .qsf setting that would work for the Sx.

I will not change the FPGA, I could prototype all ASIC for the last 20 Years on the Altera/Intel FPGA:

(Cyclone 3, 5, Stratix 2, 3 ,10 and Arria 10).