Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

How to vectorize/group together many signals generated from Qsys to Quartus

Hi,

In the Qsys, I am using ten input parallel ports (lets name them pio1 to pio10), each port is 12 bits. These parallel ports obtain values from the vhdl block in Quartus schematic. In the schematic bdf, I can see pio1 to pio10 from the nios ii system symbol so I can connect these pios to other blocks in my bdf.

My question is, how to vectorize these pio1 to pio10? Instead of seeing all ten pios one line by one line coming out from the Nios system symbol, what should I do in order to group all these ten pios so that I only see one instead of ten? From the one pio that I see, I can name it pio[1..10][1..12], the first bracket means pio1 to pio10, the second bracket means bit1 to bit 12 because each parallel port has 12 bits.

Could you please let me know how could I do that?

Thank you very much.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    The simplest way is to have a vector which is pio[0:119]. Where every port starts at a 12 bit offset.

    I'm pretty sure Qsys doesn't allow its connections to be 2D so while you can do it in SystemVerilog and VHDL, Qsys couldn't generate the system.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    The simplest way is to have a vector which is pio[0:119]. Where every port starts at a 12 bit offset.

    I'm pretty sure Qsys doesn't allow its connections to be 2D so while you can do it in SystemVerilog and VHDL, Qsys couldn't generate the system.

    --- Quote End ---

    TCWORLD, thank you for your reply.

    At the VHDL side, I have no problem to make it vector.

    Forgive me, I don't understand how to set pio[0:119] in Qsys as I can only set a maximum of 32 bits for each pio in Qsys, please could you explain in details how I could achieve pio[0:119]?

    Thank you in advance.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    You make another 'helper' IP core.

    Essentially create a Verilog of VHDL file like: 

    
module pio_helper(
 input  pio1,
 ...
 output  piomerge
);
assign piomerge = pio1;
...
endmodule

    Make a new component in Qsys using that module, and connect all your pio controllers to it. Then export the larger merged output from your Qsys system.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    You make another 'helper' IP core.

    Essentially create a Verilog of VHDL file like: 

    
module pio_helper(
 input  pio1,
 ...
 output  piomerge
);
assign piomerge = pio1;
...
endmodule

    Make a new component in Qsys using that module, and connect all your pio controllers to it. Then export the larger merged output from your Qsys system.

    --- Quote End ---

    Thank you again for your reply.

    I have a few questions:

    1. when you said "make a new component", does it mean I have to make custom made component in Qsys where I need to assign the variables writeenable, chipselect etc??

    2. where do I get the pio controllers?

    3. could you please provide me relevant resources to learn about this 'helper' IP core? I assume 'helper' IP core is not common name? where can I see examples of doing it in vhdl and Qsys?

    Thank you again for your kind replies.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    You make another 'helper' IP core.

    Essentially create a Verilog of VHDL file like: 

    
module pio_helper(
 input  pio1,
 ...
 output  piomerge
);
assign piomerge = pio1;
...
endmodule

    Make a new component in Qsys using that module, and connect all your pio controllers to it. Then export the larger merged output from your Qsys system.

    --- Quote End ---

    Hi TCWORLD,

    Could you please please explain further? I have made the code so that only ONE line coming out from the vhdl block pio[1..10][1..12] , but in the Nios II symbol generated by Qsys, I can't make it 2D, so I have 12 lines, pio[1][1..12], pio[2][1..12] until pio[10][1..12]... what should I do next so that I will only have ONE line from Nios II symbol??
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    You make another 'helper' IP core.

    Essentially create a Verilog of VHDL file like: 

    
module pio_helper(
 input  pio1,
 ...
 output  piomerge
);
assign piomerge = pio1;
...
endmodule

    Make a new component in Qsys using that module, and connect all your pio controllers to it. Then export the larger merged output from your Qsys system.

    --- Quote End ---

    Hi TCWORLD,

    I have made the code so that only ONE line coming out from the vhdl block pio[1..10][1..12] , but in the Nios II symbol generated by Qsys, I can't make it 2D, so I have 12 lines, pio[1][1..12], pio[2][1..12] until pio[10][1..12]... what should I do next so that I will only have ONE line from Nios II symbol??

    As mentioned in your post, I have already created a .vhdl file as follows:

    entity pio_helper is

    port(

    pio1 : in std_logic_vector(11 downto 0);

    pio2 : in std_logic_vector(11 downto 0);

    pio3 : in std_logic_vector(11 downto 0);

    pio4 : in std_logic_vector(11 downto 0);

    pio5 : in std_logic_vector(11 downto 0);

    pio6 : in std_logic_vector(11 downto 0);

    pio7 : in std_logic_vector(11 downto 0);

    pio8 : in std_logic_vector(11 downto 0);

    pio9 : in std_logic_vector(11 downto 0);

    pio10 : in std_logic_vector(11 downto 0);

    pio11 : in std_logic_vector(11 downto 0);

    pio12 : in std_logic_vector(11 downto 0);

    piomerge : out std_logic_vector(143 downto 0)

     );

    end pio_helper;

    architecture behavior of pio_helper is

    begin

    piomerge(11 downto 0) <= pio1;

    piomerge(23 downto 12) <= pio2;

    piomerge(35 downto 24) <= pio3;

    piomerge(47 downto 36) <= pio4;

    piomerge(59 downto 48) <= pio5;

    piomerge(71 downto 60) <= pio6;

    piomerge(83 downto 72) <= pio7;

    piomerge(95 downto 84) <= pio8;

    piomerge(107 downto 96) <= pio9;

    piomerge(119 downto 108) <= pio10;

    piomerge(131 downto 120) <= pio11;

    piomerge(143 downto 132) <= pio12;

    end behavior;

    I have created a new component in Qsys using this pio_helper.vhd file,

    My question is, how do I access each pio1, pio2...pio12 etc in C code? since conduit component is not assigned base address?