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Altera_Forum
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11 years ago

How to vectorize/group together many signals generated from Qsys to Quartus

Hi, In the Qsys, I am using ten input parallel ports (lets name them pio1 to pio10), each port is 12 bits. These parallel ports obtain values from the vhdl block in Quartus schematic. In the s...
Altera_Forum's avatar
Altera_Forum
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11 years ago

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The simplest way is to have a vector which is pio[0:119]. Where every port starts at a 12 bit offset.

I'm pretty sure Qsys doesn't allow its connections to be 2D so while you can do it in SystemVerilog and VHDL, Qsys couldn't generate the system.

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TCWORLD, thank you for your reply.

At the VHDL side, I have no problem to make it vector.

Forgive me, I don't understand how to set pio[0:119] in Qsys as I can only set a maximum of 32 bits for each pio in Qsys, please could you explain in details how I could achieve pio[0:119]?

Thank you in advance.