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You make another 'helper' IP core.
Essentially create a Verilog of VHDL file like:
module pio_helper(
input pio1,
...
output piomerge
);
assign piomerge = pio1;
...
endmodule
Make a new component in Qsys using that module, and connect all your pio controllers to it. Then export the larger merged output from your Qsys system.
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Hi TCWORLD,
I have made the code so that only ONE line coming out from the vhdl block pio[1..10][1..12] , but in the Nios II symbol generated by Qsys, I can't make it 2D, so I have 12 lines, pio[1][1..12], pio[2][1..12] until pio[10][1..12]... what should I do next so that I will only have ONE line from Nios II symbol??
As mentioned in your post, I have already created a .vhdl file as follows:
entity pio_helper is
port(
pio1 : in std_logic_vector(11 downto 0);
pio2 : in std_logic_vector(11 downto 0);
pio3 : in std_logic_vector(11 downto 0);
pio4 : in std_logic_vector(11 downto 0);
pio5 : in std_logic_vector(11 downto 0);
pio6 : in std_logic_vector(11 downto 0);
pio7 : in std_logic_vector(11 downto 0);
pio8 : in std_logic_vector(11 downto 0);
pio9 : in std_logic_vector(11 downto 0);
pio10 : in std_logic_vector(11 downto 0);
pio11 : in std_logic_vector(11 downto 0);
pio12 : in std_logic_vector(11 downto 0);
piomerge : out std_logic_vector(143 downto 0)
);
end pio_helper;
architecture behavior of pio_helper is
begin
piomerge(11 downto 0) <= pio1;
piomerge(23 downto 12) <= pio2;
piomerge(35 downto 24) <= pio3;
piomerge(47 downto 36) <= pio4;
piomerge(59 downto 48) <= pio5;
piomerge(71 downto 60) <= pio6;
piomerge(83 downto 72) <= pio7;
piomerge(95 downto 84) <= pio8;
piomerge(107 downto 96) <= pio9;
piomerge(119 downto 108) <= pio10;
piomerge(131 downto 120) <= pio11;
piomerge(143 downto 132) <= pio12;
end behavior;
I have created a new component in Qsys using this pio_helper.vhd file,
My question is, how do I access each pio1, pio2...pio12 etc in C code? since conduit component is not assigned base address?
Honored Contributor
