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Altera_Forum's avatar
Altera_Forum
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11 years ago

How to vectorize/group together many signals generated from Qsys to Quartus

Hi, In the Qsys, I am using ten input parallel ports (lets name them pio1 to pio10), each port is 12 bits. These parallel ports obtain values from the vhdl block in Quartus schematic. In the s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

You make another 'helper' IP core.

Essentially create a Verilog of VHDL file like: 


module pio_helper(
 input  pio1,
 ...
 output  piomerge
);
assign piomerge = pio1;
...
endmodule

Make a new component in Qsys using that module, and connect all your pio controllers to it. Then export the larger merged output from your Qsys system.