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You make another 'helper' IP core.
Essentially create a Verilog of VHDL file like:
module pio_helper(
input pio1,
...
output piomerge
);
assign piomerge = pio1;
...
endmodule
Make a new component in Qsys using that module, and connect all your pio controllers to it. Then export the larger merged output from your Qsys system.
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Thank you again for your reply.
I have a few questions:
1. when you said "make a new component", does it mean I have to make custom made component in Qsys where I need to assign the variables writeenable, chipselect etc??
2. where do I get the pio controllers?
3. could you please provide me relevant resources to learn about this 'helper' IP core? I assume 'helper' IP core is not common name? where can I see examples of doing it in vhdl and Qsys?
Thank you again for your kind replies.
Honored Contributor
