How to use Shared Variable

The main use for shared variables is in test benches

have a look at OSVVM. ORG

the free packages there make extensive use of SHARED VARIABLES

They are also very useful verification packages.

creating good stimulus is often a lot of work & is boring.

SAVE YOURSELF A LOT OF WORK

have a look at intelligent coverage at OSVVM. ORG

Those packages can create intelligent random functional coverage stimulus for you.

With very little effort from you they can create stimulus for all the functions you ask them to cover in your testbench.

The OSVVM packages are written by Jim Lewis & he leads the IEEE VHDL standard group who are working on the next version of VHDL after VHDL2008.

Thank

Is any other person have OSVVM opinion

A shared variable is just a variable that can be used in several processes, similar to a signal, but it will update immediately.

In VHDL 93, they could be declared for any type, but in 2002 onwards shared variables must be a protected type. (this rule is ignored by default in modelsim/quartus to maintain backwards compatability).

Shared variables can be used to infer write-before read behaviour in infered rams rather than using a signal.

On the testbenching side - they can be used with protected types (like OSVVM) so that you have variables with some behaviour simular to OO programming, although there are many restrictions.

What are you goals, as this is a very open question. In FPGAs, they are most often used for ram behaviour inference, as I specified above.

Be warned though, if used incorrectly, they can become prone to compile order dependency. Consisder the following:

shared variable a : std_logic;
process(clk)
begin
  if rising_edge(clk) then
    a := '1';
  end if;
end process;
process(clk)
begin
  if rising_edge(clk) then
    a := '0';
  end if;
end process;

here, you have no idea if "a" will end up as '1' or '0', as you do not know which process will act on the variable last. There are no 'X' values to denote unknown in simulation as its down to the compiler which process "wins". (quartus will throw multiple driver error though)

Thank tricky good info

Is any other person have opinion

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Thank tricky good info

Is any other person have opinion

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As for an opinion - just dont use them in synthesisable code. Stick to signals like everyone else.

As I said above

The main use for shared variables is in test benches

the free OSVVM packages make extensive use of SHARED VARIABLES

You will find this webinar very useful

https://www.doulos.com/content/events/adv_vhdl_verification.php

Here is another OSVVM Shared Variable Webinar Link for You

I was going to post it last week but I couldn't find it.

This shows how VERY useful Shared Variables can be in testbenches.

www.aldec.com/en/support/resources/multimedia/webinars/1719

Thank Tricky

thank DoItRight

2 webinar you link GOOD GOOD GOOD

see good info in 2 webinar

In what context are you looking at?

There is NO REASON to use a shared variable in synthesis code - other than for a write-before read ram inference

There are loads of reasons to use them in testbenches.

What are you trying to do?