How to use Shared Variable

A shared variable is just a variable that can be used in several processes, similar to a signal, but it will update immediately.

In VHDL 93, they could be declared for any type, but in 2002 onwards shared variables must be a protected type. (this rule is ignored by default in modelsim/quartus to maintain backwards compatability).

Shared variables can be used to infer write-before read behaviour in infered rams rather than using a signal.

On the testbenching side - they can be used with protected types (like OSVVM) so that you have variables with some behaviour simular to OO programming, although there are many restrictions.

What are you goals, as this is a very open question. In FPGAs, they are most often used for ram behaviour inference, as I specified above.

Be warned though, if used incorrectly, they can become prone to compile order dependency. Consisder the following:

shared variable a : std_logic;
process(clk)
begin
  if rising_edge(clk) then
    a := '1';
  end if;
end process;
process(clk)
begin
  if rising_edge(clk) then
    a := '0';
  end if;
end process;

here, you have no idea if "a" will end up as '1' or '0', as you do not know which process will act on the variable last. There are no 'X' values to denote unknown in simulation as its down to the compiler which process "wins". (quartus will throw multiple driver error though)