Forum Discussion
Vicky1
Regular Contributor
6 years agoHi Balakrishna,
After successfully synthesis(my last post) , instantiate it in top module like below,
- Open .bdf file
- File-> Create/Update->Create VHDL component declaration component files for current file(It will create .cmp file)
- Open that .cmp file & instantiate it in top module & then compile that top module.
Regards,
Vicky