How to use Avalon-MM Master BFM?

Hi Joel,

These errors are because Altera has changed the way the SystemVerilog is compiled into libraries (the library names have changed). I was writing an Avalon-MM master/slave example last night to understand how to use the Avalon-MM burstcount interface. I'll finish that today, and then post it to this thread. I also need to update the tutorial with the latest steps for compilation.

Cheers,

Dave

Here's a quick solution to your error above:

Look in msim_setup.tcl and determine what library verbosity_pkg and avalon_mm_pkg are compiled into; in my case the code was compiled into both master_bfm and slave_bfm libraries (which correspond to the Qsys names I used in the example I am currently working on - your library name may be different).

Change the -L argument to vcom to match one of these libraries, and the packages will be resolved.

This is one of the "errors" in the Modelsim scripts created by Altera tools. The verification components should be compiled into a common library, eg., altera_verification_ip, not into multiple libraries that are based on the component names.

For example, if I compile using -L slave_bfm, then using the REQ_READ enumeration to the master API generates an error, since it resolves to an enumeration in the slave_bfm library ... argh! I'll edit msim_setup.tcl to create a common library and see if that helps ...

Update: I modified all the pointlessly named libraries in the msim_setup.tcl script to compile into the library "altera_verification" and then passed -L altera_verification to the compilation of the top-level testbench and to the simulation command, and now the data types in these packages resolve correctly.

I'll post code once I get my master/slave example completed.

Cheers,

Dave

The attached file contains a Qsys system with an Avalon-MM Master BFM and an Avalon-MM Slave BFM. The testbench uses the Master BFM to issue single write/read and burst write/read transactions to the Slave BFM.

The readme.txt file describes how to build the system from scratch using Quartus and Qsys, and then indicates the edits that need to be made to the Modelsim simulation script (msim_setup.tcl) to simulate the top-level testbench. The readme.txt file indicates the differences between Quartus 12.1sp1 and Quartus 13.1. The Modelsim setup script is much better under Quartus 13.1 (less edits required).

Cheers,

Dave

Hi Dave,

Tried the zip file and it worked for me using Quartus 13.1! The library naming was really weird from Altera. It's a big problem for someone who's trying to learn qsys and verif.

Thanks again! Extremely helpful!

r/joel

Hi Joel,

--- Quote Start ---

Thanks again! Extremely helpful!

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You're welcome.

I'm glad to hear you got it working.

Cheers,

Dave

Hi,

I followed the tutorial in setting up the Avalom MM Master BFM simulation to work. I got the following error when I compile:

# ** Error: (vsim-8386) ./av_mm_master_test_program.sv(45): Illegal assignment to type 'avalon_mm_pkg.enum int ' from type '[email protected] int ': An enum variable may only be assigned the same enum typed variable or one of its values.

I used the read/write tasks from the tutorial. Any ideas what may be the issue here? Thanks.

`timescale 1 ps / 1 psmodule test_program();import verbosity_pkg::*;import avalon_mm_pkg::*;//console messaging level`define VERBOSITY VERBOSITY_INFO//bfm hierachy`define CLK_BFM top.tb.pcie_de_gen1_x4_ast64_inst_clk_bfm`define RST_BFM top.tb.pcie_de_gen1_x4_ast64_inst_reset_bfm`define MM_MASTER top.tb.pcie_de_gen1_x4_ast64_inst.mm_master_bfm_0//`define av_address_w 32//`define av_data_w 32//parameter av_address_w = 32;//parameter av_data_w = 32; // ============================================================ // tasks // ============================================================ // // avalon-mm single-transaction read and write procedures. // // ------------------------------------------------------------ task avalon_write ( // ------------------------------------------------------------// input logic [av_address_w-1:0] addr,// input logic [av_data_w-1:0] data input logic [31:0] addr, input logic [31:0] data ); begin //bit [av_address_w-1:0] addr_int; //addr_int = addr; // construct the bfm request `MM_MASTER.set_command_request(REQ_WRITE); `MM_MASTER.set_command_idle(0, 0); `MM_MASTER.set_command_init_latency(0); `MM_MASTER.set_command_address(addr); `MM_MASTER.set_command_byte_enable('1,0); `MM_MASTER.set_command_data(data, 0); // queue the command `MM_MASTER.push_command(); // wait until the transaction has completed while (`MM_MASTER.get_response_queue_size() != 1) @(posedge `CLK_BFM.clk); // dequeue the response and discard `MM_MASTER.pop_response(); end endtask // ------------------------------------------------------------ task avalon_read ( // ------------------------------------------------------------// input logic [av_address_w-1:0] addr,// output logic [av_data_w-1:0] data input logic [31:0] addr, output logic [31:0] data ); begin //bit [av_address_w-1:0] addr_int; //addr_int = addr; // construct the bfm request `MM_MASTER.set_command_request(REQ_READ); `MM_MASTER.set_command_idle(0, 0); `MM_MASTER.set_command_init_latency(0); `MM_MASTER.set_command_address(addr); `MM_MASTER.set_command_byte_enable('1,0); `MM_MASTER.set_command_data(0, 0); // queue the command `MM_MASTER.push_command(); // wait until the transaction has completed while (`MM_MASTER.get_response_queue_size() != 1) @(posedge `CLK_BFM.clk); // dequeue the response and return the data `MM_MASTER.pop_response(); data = `MM_MASTER.get_response_data(0); endendtask event start_test; event end_test; //---------------------------------------------------------------------------------- // set verbosity before the test starts // qsys-generated testbench activates clock and reset bmfs //---------------------------------------------------------------------------------- initial begin set_verbosity(`VERBOSITY); // initialize bfms `MM_MASTER.init(); end //---------------------------------------------------------------------------------- // main test block //---------------------------------------------------------------------------------- initial begin // wait for reset inactive wait(`RST_BFM.reset == 1); -> start_test; end initial begin // @ start_test; // start write access/* `mm_master.set_command_request(req_write); `mm_master.set_command_address(16'h0); `mm_master.set_command_idle(2,0); `mm_master.set_command_init_latency(0); `mm_master.set_command_data(32'h0,0); `mm_master.push_command();*/ avalon_write (32'h00000000, 32'haaaabbbb ); end endmodule

Hi in the tutorial by David , am having problem in section 4.5.2 Avalon-MM Master BFM.

when i perform the following step

Compile the tutorial testbench

ModelSim> vlog -sv $TUTORIAL/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv

-L qsys_system_bfm_master

i get this error:

# Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009

# -- Compiling module qsys_system_bfm_master_tb

# ** Error: c:/temp/altera_jtag_to_avalon_mm_tutorial/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv(48): Could not find the package (verbosity_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.

# ** Error: c:/temp/altera_jtag_to_avalon_mm_tutorial/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv(49): Could not find the package (avalon_mm_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.

# C:/altera/91/modelsim_ase/win32aloem/vlog failed.

-L qsys_system_bfm_master

# invalid command name "-L"

i have tried whatever i could , but not able to proceed. Can someone help ?

Thanks in Advance!

This is exactly the same question as asked at the top of this forum page by Joel, to which I answered with the qsys_vip.zip a few posts above. Unfortunately Altera have changed the way they include the libraries in 13.1.

I recommend you unzip that file and read the instructions that it includes.

Cheers,

Dave

Hi all,

For my previous post, I couldn't get the solution given by david for joel working as my model sim is only 6.5 version. I'Ll download the latest and try the solution.

Thanks!