How to use Avalon-MM Master BFM?

Hi,

I followed the tutorial in setting up the Avalom MM Master BFM simulation to work. I got the following error when I compile:

# ** Error: (vsim-8386) ./av_mm_master_test_program.sv(45): Illegal assignment to type 'avalon_mm_pkg.enum int ' from type 'avalon_mm_pkg@work.enum int ': An enum variable may only be assigned the same enum typed variable or one of its values.

I used the read/write tasks from the tutorial. Any ideas what may be the issue here? Thanks.

`timescale 1 ps / 1 psmodule test_program();import verbosity_pkg::*;import avalon_mm_pkg::*;//console messaging level`define VERBOSITY VERBOSITY_INFO//bfm hierachy`define CLK_BFM top.tb.pcie_de_gen1_x4_ast64_inst_clk_bfm`define RST_BFM top.tb.pcie_de_gen1_x4_ast64_inst_reset_bfm`define MM_MASTER top.tb.pcie_de_gen1_x4_ast64_inst.mm_master_bfm_0//`define av_address_w 32//`define av_data_w 32//parameter av_address_w = 32;//parameter av_data_w = 32; // ============================================================ // tasks // ============================================================ // // avalon-mm single-transaction read and write procedures. // // ------------------------------------------------------------ task avalon_write ( // ------------------------------------------------------------// input logic [av_address_w-1:0] addr,// input logic [av_data_w-1:0] data input logic [31:0] addr, input logic [31:0] data ); begin //bit [av_address_w-1:0] addr_int; //addr_int = addr; // construct the bfm request `MM_MASTER.set_command_request(REQ_WRITE); `MM_MASTER.set_command_idle(0, 0); `MM_MASTER.set_command_init_latency(0); `MM_MASTER.set_command_address(addr); `MM_MASTER.set_command_byte_enable('1,0); `MM_MASTER.set_command_data(data, 0); // queue the command `MM_MASTER.push_command(); // wait until the transaction has completed while (`MM_MASTER.get_response_queue_size() != 1) @(posedge `CLK_BFM.clk); // dequeue the response and discard `MM_MASTER.pop_response(); end endtask // ------------------------------------------------------------ task avalon_read ( // ------------------------------------------------------------// input logic [av_address_w-1:0] addr,// output logic [av_data_w-1:0] data input logic [31:0] addr, output logic [31:0] data ); begin //bit [av_address_w-1:0] addr_int; //addr_int = addr; // construct the bfm request `MM_MASTER.set_command_request(REQ_READ); `MM_MASTER.set_command_idle(0, 0); `MM_MASTER.set_command_init_latency(0); `MM_MASTER.set_command_address(addr); `MM_MASTER.set_command_byte_enable('1,0); `MM_MASTER.set_command_data(0, 0); // queue the command `MM_MASTER.push_command(); // wait until the transaction has completed while (`MM_MASTER.get_response_queue_size() != 1) @(posedge `CLK_BFM.clk); // dequeue the response and return the data `MM_MASTER.pop_response(); data = `MM_MASTER.get_response_data(0); endendtask event start_test; event end_test; //---------------------------------------------------------------------------------- // set verbosity before the test starts // qsys-generated testbench activates clock and reset bmfs //---------------------------------------------------------------------------------- initial begin set_verbosity(`VERBOSITY); // initialize bfms `MM_MASTER.init(); end //---------------------------------------------------------------------------------- // main test block //---------------------------------------------------------------------------------- initial begin // wait for reset inactive wait(`RST_BFM.reset == 1); -> start_test; end initial begin // @ start_test; // start write access/* `mm_master.set_command_request(req_write); `mm_master.set_command_address(16'h0); `mm_master.set_command_idle(2,0); `mm_master.set_command_init_latency(0); `mm_master.set_command_data(32'h0,0); `mm_master.push_command();*/ avalon_write (32'h00000000, 32'haaaabbbb ); end endmodule