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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to use Avalon-MM Master BFM?

Hello, all.

I want to use Avalon Verification IP Suite to check a Qsys custom componet, which have an Avalon salve interface and a Avalon conduit interface connecting a LSI.

I wrote this program to test if the custom component can give right response to the Avalon Master BFM. 


//Console messaging level
`define VERBOSITY VERBOSITY_INFO
//BFM hierachy
`define CLK_BFM     top.tb.clock_source
`define RST_BFM     top.tb.reset_source
`define MM_MASTER   top.tb.avalon_mm_master
`define CONDUIT_BFM top.tb.conduit_bfm
module test_program();
  import verbosity_pkg::*;
  import avalon_mm_pkg::*;
  
  event start_test;
  event end_test;
  
  //----------------------------------------------------------------------------------
  // Set verbosity before the test starts
  // Qsys-generated testbench activates clock and reset BMFs
  //----------------------------------------------------------------------------------
  initial begin
	set_verbosity(`VERBOSITY);
	
	// initialize BFMS
	`MM_MASTER.init();
  end
  
  //----------------------------------------------------------------------------------
  // Main test block
  //----------------------------------------------------------------------------------
  initial begin
	// wait for reset inactive
	wait(`RST_BFM.reset == 1);
		-> start_test;
  end
  
  initial begin 
	@ start_test;
	// start write access
	`MM_MASTER.set_command_request(REQ_WRITE);
	`MM_MASTER.set_command_address(16'h0);
	`MM_MASTER.set_command_idle(2,0);
	`MM_MASTER.set_command_init_latency(0);
	`MM_MASTER.set_command_data(32'h0,0);
		
	`MM_MASTER.push_command();
  end
  
endmodule

Although this program can be compiled by ModelSim with no error, but it seems the write access was not started.

Can you give me some hints or some examples about how to test custom components wit Avalon IP verification suite?

Regards,

feng

51 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi feng,

    Your code enqueues a transaction, but it does not wait for it to complete, so Modelsim exits too soon. Here's a couple of tasks I use: 

    
    // ============================================================
    // Tasks
    // ============================================================
    //
    // Avalon-MM single-transaction read and write procedures.
    //
    // ------------------------------------------------------------
    task avalon_write (
    // ------------------------------------------------------------
        input  addr,
        input     data
    );
    begin
        // Construct the BFM request
        `BFM.set_command_request(REQ_WRITE);
        `BFM.set_command_idle(0, 0);
        `BFM.set_command_init_latency(0);
        `BFM.set_command_address(addr);    
        `BFM.set_command_byte_enable('1,0);
        `BFM.set_command_data(data, 0);      
        // Queue the command
        `BFM.push_command();
        
        // Wait until the transaction has completed
        while (`BFM.get_response_queue_size() != 1)
            @(posedge clk);
        // Dequeue the response and discard
        `BFM.pop_response();
    end
    endtask
            
    // ------------------------------------------------------------
    task avalon_read (
    // ------------------------------------------------------------
        input   addr,
        output     data
    );
    begin
        // Construct the BFM request
        `BFM.set_command_request(REQ_READ);
        `BFM.set_command_idle(0, 0);
        `BFM.set_command_init_latency(0);
        `BFM.set_command_address(addr);    
        `BFM.set_command_byte_enable('1,0);
        `BFM.set_command_data(0, 0);      
        // Queue the command
        `BFM.push_command();
        
        // Wait until the transaction has completed
        while (`BFM.get_response_queue_size() != 1)
            @(posedge clk);
        // Dequeue the response and return the data
        `BFM.pop_response();
        data = `BFM.get_response_data(0);        
    end
    endtask

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Hi feng,

    Your code enqueues a transaction, but it does not wait for it to complete, so Modelsim exits too soon. Here's a couple of tasks I use: 

    
    // ============================================================
    // Tasks
    // ============================================================
    //
    // Avalon-MM single-transaction read and write procedures.
    //
    // ------------------------------------------------------------
    task avalon_write (
    // ------------------------------------------------------------
        input  addr,
        input     data
    );
    begin
        // Construct the BFM request
        `BFM.set_command_request(REQ_WRITE);
        `BFM.set_command_idle(0, 0);
        `BFM.set_command_init_latency(0);
        `BFM.set_command_address(addr);    
        `BFM.set_command_byte_enable('1,0);
        `BFM.set_command_data(data, 0);      
        // Queue the command
        `BFM.push_command();
        
        // Wait until the transaction has completed
        while (`BFM.get_response_queue_size() != 1)
            @(posedge clk);
        // Dequeue the response and discard
        `BFM.pop_response();
    end
    endtask
            
    // ------------------------------------------------------------
    task avalon_read (
    // ------------------------------------------------------------
        input   addr,
        output     data
    );
    begin
        // Construct the BFM request
        `BFM.set_command_request(REQ_READ);
        `BFM.set_command_idle(0, 0);
        `BFM.set_command_init_latency(0);
        `BFM.set_command_address(addr);    
        `BFM.set_command_byte_enable('1,0);
        `BFM.set_command_data(0, 0);      
        // Queue the command
        `BFM.push_command();
        
        // Wait until the transaction has completed
        while (`BFM.get_response_queue_size() != 1)
            @(posedge clk);
        // Dequeue the response and return the data
        `BFM.pop_response();
        data = `BFM.get_response_data(0);        
    end
    endtask

    Cheers,

    Dave

    --- Quote End ---

    I solved the problem using your tasks. Thanks, Dave.

    And I have another question. This custom component has an Avalon conduit interface connecting a LSI. I read the Conduit BFM section, and didn't find the right function.

    Can you tell me how to set the values of signals from the LSI?

    Best regards,

    feng
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    I solved the problem using your tasks. Thanks, Dave.

    --- Quote End ---

    Great!

    --- Quote Start ---

    And I have another question. This custom component has an Avalon conduit interface connecting a LSI. I read the Conduit BFM section, and didn't find the right function.

    Can you tell me how to set the values of signals from the LSI?

    --- Quote End ---

    Don't use their test_bench() module, use your own. Lets say your design is called sopc_system, then sopc_system.v contains a module called test_bench() at the end of it. Copy the contents of that testbench into your top-level testbench, and adjust the path to the BFM accordingly. Then drive or read the conduit interfaces on the sopc_system module directly.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks for your reply, Dave.

    I'm using Quartus II 11.0 Web Edition, and I can't find the test_bench() module in my design file. Is the test_bench() module produced automatically by Qsys?

    Regards,

    feng
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    I'm using Quartus II 11.0 Web Edition, and I can't find the test_bench() module in my design file. Is the test_bench() module produced automatically by Qsys?

    --- Quote End ---

    Yes. Look at your own code ...

    `define CLK_BFM top.tb.clock_source

    The 'tb' entry in that hierarchy is the test_bench() component you want to copy and eliminate from the design. You'll copy the clock generator, the reset generator, and the Qsys system instance, and then you will have access to the ports on the Qsys system instance, so you can manipulate the exported ports.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    I'll try that.

    --- Quote End ---

    Use the Modelsim GUI to navigate to the component in the hierarchy. It'll tell you what file its in (you might be able to double-click to bring the file into the Modelsim editor).

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Really thanks for your reply, Dave.

    Because I'm not familiar with ModelSim, so I don't know how to navigate to component. But I can find the files in my design folder.

    Regards,

    feng
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hello,

    this problem looks to be solved. My problem is very similar, so I don't want to start a new topic for my question.

    I would like to use 2 Avalon MM BFMs in my Simulation. First BFM should write data, the second one - read data. It is not difficult to get the simulation running with one BFM is doing both tasks, but what should I do differently to get 2 BFMS running?

    Let's say, that my BFMs are defined as:

    `define FIRST_BFM tb.simulation_inst.mm_master_bfm_0

    `define SEC_BFM tb.simulation_inst.mm_master_bfm_1

    When I change the write task to use SEC_BFM instead of FIRST_BFM I got this error and simulation fails:# 416198192: FAILURE: top.tb.simulation_inst.mm_master_bfm_1.request_timeout.timeout_thread: Command phase timeout