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I'm using Quartus II 11.0 Web Edition, and I can't find the test_bench() module in my design file. Is the test_bench() module produced automatically by Qsys?
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Yes. Look at your own code ...
`define CLK_BFM top.tb.clock_source
The 'tb' entry in that hierarchy is the test_bench() component you want to copy and eliminate from the design. You'll copy the clock generator, the reset generator, and the Qsys system instance, and then you will have access to the ports on the Qsys system instance, so you can manipulate the exported ports.
Cheers,
Dave
Honored Contributor
