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JPowe1
New Contributor
New ContributorHow to tell timing closure is achieved? How to create real timing constraints?
I'm working on a Max 10 FPGA that implements a SPI master and a Manchester encoder/decoder. The decoder looks for transitions in the middle of each bit to recover the data clock. The SPI clock is 1/...
IDeyn
Contributor
ContributorHi JPowe1!
First of all, SCK is not a true clock because of it's duty cycle, which is not constant.
Secondly, I think you can simply write set_false_paths for TQuest to ignore the timing if you are sure that timing is valid because your SPI and Manchester clocks are low speed compared to FPGA clock.
Hope that helps.
Best regards,
Ivan
