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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to specify transceiver block for PCIe x4 HIP?

Hi Experts,

I try to run PCI Express High Performance Reference Design on my custom board.

I'm using PCIe x4 HIP on an EP2AGX45 chip.

Due to my board design, I have to assign tx_in[3..0] and tx_out[3..0] to QL1.

During compilation, fitter gives the following error message:

Error: Can't assign I/O pad "tx_out0" to PIN_V25 because this causes failure in the placement of the other atoms in its associated channel

Error: Atom top_example_chaining_pipen1b:core|top_plus:ep_plus|top:epmap|top_serdes:serdes|top_serdes_alt4gxb_uj9b:top_serdes_alt4gxb_uj9b_component|receive_pma0 cannot be constrained to location RXPMA_X0_Y27_N137 because the channel number is 0, corresponding to the HIP top_example_chaining_pipen1b:core|top_plus:ep_plus|top:epmap|top_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|arria_ii.arriaii_hssi_pcie_hip lane number 4, which is inactive due to the lane mask

......

Where can I specify the transceiver block for the x4 HIP? Thanks!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    it looks like you're trying to use a x4 PCIe but you're trying to use the upper half of the x8 HIP block ("lane number 4, which is inactive due to the lane mask"). i'm not sure if this is a legal configuration

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi thepancake,

    Thank you for your reply.

    I've searched pci express compiler user guide and arria ii gx handbook but could not find whether it's illegal to use QL1 for a PCIe x4 HIP.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    it may not be explicitly documented, but i suspect that's the issue