how to simulation tristate bus in modelsim

Could someone let me know if there is a way that I can use a testbench in modelsim to drive a signal into an external tristate bus. I am using vhdl with the bus defined as type inout at the top level, and I would like to include it as part of my testbench. If I try to set a value to the bus while the internal value is Z, the destination signal also gets set to Z rather than the value set by the testbench.

Thanks.