Honored Contributor
Honored Contributorhow did I do it in VHDL? Possible, it will useful some people.
1) Generate new project where assignment-settings-simulation format for output netlist set to VHDL 2) Create top-level file (see main below) 3) tools-megawizard plugin, generate our PLL, for example: in 25MHz, out - 100MHz 4) Compile, processing-start-start analysis and elaboration, next tools-run eda simulation - gate level 5) In Modelsim expand "work", select our module (x_pll), create dummy wave and delete all output signals. 6) right click on module, select 'Simulate' and now draw real waves. If try do it on previous step, MS mixed ns and ps. 7) drag-n-drop output signals to wave window. Correct run lenght 100 ps to 1 ps - this one I'm not sure. 8) menu simulate-run-run -all It is done! If somebody can give me advise how to optimize it - I will glade. If I choose system verilog and 1 ps on step# 1 - ModelSim lost libraries! 2 tricky: You are right - I need clock. how correct do it? And - I have done it for VHDL but how to do the same for schematic I don't know still.-- Try to simulate PLL
-- t.oleg(a)ymail.com
library ieee;
use ieee.std_logic_1164.all;
entity x_pll is
PORT(
x_clk: in std_logic;
x_rst: in std_logic;
x_c0: out std_logic;
x_lock: out std_logic );
end entity;
architecture RTL of x_pll is
component amf_pll
PORT(
areset: in std_logic;
inclk0: in std_logic;
c0: out std_logic;
locked: out std_logic );
end component;
signal c0_sig, i_locked: std_logic;
begin
pll_mf: amf_pll PORT MAP (
areset => x_rst,
inclk0 => x_clk,
c0 => c0_sig,
locked => i_locked
);
x_lock <= i_locked;
x_c0 <= c0_sig when (i_locked='1') else '0';
end RTL;
